QoS is defined for the PL340 DMC as a method of increasing the arbitration priority of a read access that requires low-latency read data. See Arbitration for more information. The QoS for an AXI read access is determined when the arbiter receives it. No QoS exists for write accesses. There are two forms of QoS tracking:

In addition, the qos_override function can dynamically force a qos_min flag for an entry.

The allocation of QoS functionality is determined by the ARID of the entry compared with a 4-bit selection mask defined by the qos_master_bits in the memory_cfg Register. The 4-bits selected can be any four contiguous bits from up to eight ARID bits, that is, [3:0], [4:1], [5:2], [6:3], or [7:4].

The resultant 4-bit QoS selection number is compared against the qos_override ports that QoS interface describes, and also enables 16 separate programmable QoS options, that the 16 id_<n>_cfg Registers. See id_<n>_cfg Registers.

If the QoS enable bit for the ARID is set in the register bank, the QoS maximum latency value is decremented every cycle until it reaches zero.

If the entry is still in the queue when the QoS maximum latency value reaches zero, then the entry becomes high priority. This is called a time-out. Also, any entry in the queue with a minimum latency QoS also produces a time-out. Minimum latency time-outs have priority over maximum latency time-outs.

When an entry times out in this way it forces a time-out onto any entries that it has dependencies against. In normal operation, these entries have already timed out because they have received the same initial QoS value, but been decrementing for longer. The highest priority arbiter entry is serviced next.

One special case exists. This is when or if the qos_override function forces a minimum latency time-out. In this instance, any accesses that the new entry has dependencies against might not have timed out and are forced to time out so that the high-priority entry can start as soon as possible.

There is also a QoS provided for the auto-refresh commands from the memory manager. The arbiter keeps track of the number of auto-refresh commands in the arbiter queue with a simple increment-decrement counter. If the number of auto-refresh commands reaches a programmable tide mark, max_out_refs, a refresh time-out is signalled to the arbiter queue. This forces all of the auto-refresh queue entries to have a time-out. This time-out is sticky, and does not disappear when the number of time-outs drops back below the threshold. Instead, it remains asserted until all of the auto-refreshes have been serviced. This provides a guaranteed refresh rate in the SDRAM.