PrimeCell ® DynamicMemory Controller (PL340) Technical Reference ManualRevision: r3p0
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PrimeCell ® DynamicMemory Controller (PL340) Technical Reference Manual

Revision: r3p0

Copyright © 2004-2007 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this memory controller
Feedback on this manual
1. Introduction
1.1. About the memory controller
1.1.1. Features of the memory controller
1.1.2. Supported memory widths
1.1.3. AXI interface attributes
1.2. Supported devices
1.3. Product revisions
2. Functional Overview
2.1. Memory controller overview
2.2. AXI slave interface
2.2.1. Memory device base address
2.2.2. Formatting AXI address channel payload
2.2.3. Exclusive access
2.3. AXI low-power interface
2.4. APB slave interface
2.5. Tie-off signals
2.6. Memory interface
2.6.1. Memory interface to pad interfacetiming
2.7. Pad interface
2.7.1. Pad interface to external memory devices
2.8. QoS interface
2.9. EBI interface
2.10. Controller management operations
2.11. Initialization
2.11.1. Example setup
2.12. Data operations
2.12.1. Hazard detection
2.12.2. Quality of Service
2.12.3. Arbitration
2.13. Low-power operation
2.13.1. System low-power control
2.13.2. Dynamic low-power mode control
2.13.3. Deep power-down
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Controller Command Register
3.3.3. Direct Command Register
3.3.4. Memory Configuration Register
3.3.5. Refresh Period Register
3.3.6. CAS Latency Register
3.3.7. t_dqss Register
3.3.8. t_mrd Register
3.3.9. t_ras Register
3.3.10. t_rc Register
3.3.11. t_rcd Register
3.3.12. t_rfc Register
3.3.13. t_rp Register
3.3.14. t_rrd Register
3.3.15. t_wr Register
3.3.16. t_wtr Register
3.3.17. t_xp Register
3.3.18. t_xsr Register
3.3.19. t_esr Register
3.3.20. memory_cfg2 Register
3.3.21. memory_cfg3 Register
3.3.22. id_<n>_cfg Registers
3.3.23. chip_<n>_cfg Registers
3.3.24. user_status Register
3.3.25. user_config Register
3.3.26. Peripheral Identification Registers0-3
3.3.27. PrimeCell Identification Registers 0-3
4. Programmer’s Model for Test
4.1. Integration test registers
4.1.1. Integration Configuration Register
4.1.2. Integration Inputs Register
4.1.3. Integration Outputs Register
5. Device Driver
5.1. Device driver functions
5.1.1. Register access functions
5.1.2. Example memory initialization functions
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.3. AXI signals
A.3.1. Write address channel signals
A.3.2. Write data channel signals
A.3.3. Buffered write response channel signals
A.3.4. Read address channel signals
A.3.5. Read data channel signals
A.3.6. AXI low-power interfacesignals
A.4. APB signals
A.5. Pad interface signals
A.6. Memory Controller EBI signals
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Example system
2.1. DMC block diagram
2.2. AXI slave interface connections
2.3. AXI low-power interface channel signals
2.4. APB external connections
2.5. mclk domain FSM
2.6. Command control output timing
2.7. Activate to read or write commandtiming, tRCD
2.8. Bank activate to bank activate orauto-refresh command timing, tRC
2.9. Bank activate to different bank activatefor a memory timing, tRRD
2.10. Precharge to command and auto-refreshtiming, tRP and tRFC
2.11. Activate to precharge, and prechargeto precharge timing, tRAS and tRP
2.12. Mode register write to command timing,tMRD
2.13. Self-refresh entry and exit timing,tESR and tXSR
2.14. Power-down entry and exit timing,tXP
2.15. Data output timing, tWTR
2.16. Data output timing, tDQSS =1
2.17. Data input timing
2.18. Pad interface external connections
2.19. aclk domain state diagram
2.20. System state transitions
2.21. Auto-power-down
2.22. Force precharge with zero force prechargetime
2.23. Force precharge after pd time
2.24. Auto self-refresh entry
3.1. Register map
3.2. Memory controller configuration registermap
3.3. AXI ID configuration register map
3.4. Chip configuration registers map
3.5. Identification register map
3.6. memc_status Register bit assignments
3.7. memc_cmd Register bit assignments
3.8. direct_cmd Register bit assignments
3.9. memory_cfg Register bit assignments
3.10. refresh_prd Register bit assignments
3.11. cas_latency Register bit assignments
3.12. t_dqss Register bit assignments
3.13. t_mrd Register bit assignments
3.14. t_ras Register bit assignments
3.15. t_rc Register bit assignments
3.16. t_rcd Register bit assignments
3.17. t_rfc Register bit assignments
3.18. t_rp Register bit assignments
3.19. t_rrd Register bit assignments
3.20. t_wr Register bit assignments
3.21. t_wtr Register bit assignments
3.22. t_xp Register bit assignments
3.23. t_xsr Register bit assignments
3.24. t_esr Register bit assignments
3.25. memory_cfg2 Register bit assignments
3.26. memory_cfg3 Register bit assignments
3.27. id_<n>_cfg Registers bit assignments
3.28. chip_<n>_cfg Registers bit assignments
3.29. periph_id Register bit assignments
3.30. pcell_id Register bit assignments
4.1. Integration Test Register map
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments

List of Tables

1.1. Memory widths
1.2. Memory widths and AXI port widths
1.3. Attribute formats
2.1. Address comparison steps example
2.2. Example Mobile DDR setup
2.3. Valid system states for FSMs
2.4. Recommended power states
2.5. Dynamic low-power modes operation
3.1. Memory controller register summary
3.2. memc_status Register bit assignments
3.3. Memory banks chip configuration
3.4. memc_cmd Register bit assignments
3.5. direct_cmd Register bit assignments
3.6. memory_cfg Register bit assignments
3.7. refresh_prd Register bit assignments
3.8. cas_latency Register bit assignments
3.9. t_dqss Register bit assignments
3.10. t_mrd Register bit assignments
3.11. t_ras Register bit assignments
3.12. t_rc Register bit assignments
3.13. t_rcd Register bit assignments
3.14. t_rfc Register bit assignments
3.15. t_rp Register bit assignments
3.16. t_rrd Register bit assignments
3.17. t_wr Register bit assignments
3.18. t_wtr Register bit assignments
3.19. t_xp Register bit assignments
3.20. t_xsr Register bit assignments
3.21. t_esr Register bit assignments
3.22. memory_cfg2 Register bit assignments
3.23. memory_cfg3 Register bit assignments
3.24. id_<n>_cfg Registers bit assignments
3.25. chip_<n>_cfg Registers bit assignments
3.26. user_status Registers bit assignments
3.27. user_config Registers bit assignments
3.28. periph_id Register bit assignments
3.29. periph_id_0 Register bit assignments
3.30. periph_id_1 Register bit assignments
3.31. periph_id_2 Register bit assignments
3.32. periph_id_3 Register bit assignments
3.33. pcell_id Register bit assignments
4.1. Memory controller test register summary
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.3. Write address channel signals
A.4. Write data channel signals
A.5. Buffered write response channel signals
A.6. Read address channel signals
A.7. Read data channel signals
A.8. AXI low-power interface signals
A.9. APB signals
A.10. Pad interface signals
A.11. EBI signals

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited, except as otherwise stated below in this proprietarynotice. Other brands and names mentioned herein may be the trademarksof their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 22June 2004 First release for r0p0.
Revision B 31August 2004 Second release for r0p0.
Revision C 25August 2005 Incorporate erratum.Additional informationto Exclusive access on page 2‑6.
Revision D 09June 2006 First release for r1p0.
Revision E 16May 2007 First release for r2p0.
Revision F 30 November2007 First release for r3p0.
Copyright © 2004-2007 ARM Limited. All rights reserved. ARM DDI 0331F
Non-Confidential
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