A.2.2. Tie-offs

Table A.3 shows the tie-off signals.

Table A.3. Tie-off signals

SignalTypeSourceDescription
a_gt_m_syncInputTie-off

When aresetn is deasserted, the state of this signal sets the value of the clock_cfg [1] bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

Set this signal HIGH if aclk is greater than mclk and is synchronous.

cke_init

Input

Tie-off

When aresetn is deasserted, the state of this signal sets the value of the cke_init bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

This signal is only available when the DMC is configured to provide a legacy pad interface.

dqm_initInputTie-off

When aresetn is deasserted, the state of this signal sets the value of the dqm_init bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

This signal is only available when the DMC is configured to provide a legacy pad interface.

memory_width[1:0]

Input

Tie-off

When aresetn is deasserted, the state of this signal sets the value of the memory_width field in the memory_cfg2 Register. See Memory Configuration 2 Register.

memory_type[2:0]InputTie-off

When aresetn is deasserted, the state of this signal sets the value of the memory_protocol field in the memory_cfg2 Register. See Memory Configuration 2 Register.

You must set this signal to select a memory protocol that the configured DMC supports. The memory_protocol field shows the possible bit encodings, see Memory Configuration 2 Register.

read_delay[1:0]InputTie-off

When aresetn is deasserted, the state of this signal sets the value of the read_delay field in the memory_cfg2 Register. See Memory Configuration 2 Register.

sync

Input

Tie-off

When aresetn is deasserted, the state of this signal sets the value of the clock_cfg [0] bit in the memory_cfg2 Register. See Memory Configuration 2 Register.

Set this signal HIGH if aclk is synchronous to mclk.

Set this signal LOW if aclk is asynchronous to mclk.

use_ebi [a]InputTie-offSet this signal HIGH if the memory interface of the DMC connects to a PrimeCell External Bus Interface (PL220).

[a] This signal is not present when the DMC is configured to implement a DFI pad interface.


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