AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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A.5.2. DFI pad interface

Table A.14 shows the DFI pad interface signals. For a description of these signals, see the DDR PHY Interface (DFI) Specification .

Table A.14. DFI pad interface signals

SignalTypeSource or destination
dfi_address[15:0]OutputPHY device
dfi_bank[1:0]Output
dfi_cas_nOutput
dfi_cke[MEMORY_CHIPS-1:0][a]Output
dfi_cs_n[MEMORY_CHIPS-1:0] [a]Output
dfi_dram_clk_disable[MEMORY_CHIPS-1:0] [b]Output
dfi_init_completeInput
dfi_phyupd_ackOutput
dfi_phyupd_reqInput
dfi_phyupd_type[1:0]Input
dfi_ras_nOutput
dfi_rddata_en[MEMORY_BYTES-1:0] [b]Output
dfi_rddata[MEMWIDTH-1:0] [c]Input
dfi_rddata_valid [d]Input
dfi_we_nOutput
dfi_wrdata_en[MEMORY_BYTES-1:0] [b]Output
dfi_wrdata[MEMWIDTH-1:0] [c]Output
dfi_wrdata_mask[MEMORY_BYTES-1:0] [b]Output

[a] MEMORY_CHIPS is the number of chip selects and is set during configuration of the DMC.

[b] MEMORY_BYTES is the data width of the external memory bus in bytes and is set during configuration of the DMC.

[c] MEMWIDTH is the data width of the external memory bus in bits and is set during configuration of the DMC.


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