AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual: 4.1. Integration test registers

4.1. Integration test registers

Test registers are provided for integration testing.

Figure 4.1 shows the integration test register map.

Figure 4.1. Integration test register map

Table 4.1 shows the integration test registers in base offset order.

Table 4.1. DMC test Register summary

Offset	Name	Type	Reset	Description
`0xE00`	int_cfg	RW	`0x0`	Integration Configuration Register
`0xE04`	int_inputs	RO	-^[a]	Integration Inputs Register
`0xE08`	int_outputs	WO	-	Integration Outputs Register
^[a]Dependent on the tie-off signals.

Copyright © 2004-2007, 2009 ARM Limited. All rights reserved.	ARM DDI 0331G
Non-Confidential
PDF version