AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual: 1.1.2. Supported memory widths

1.1.2. Supported memory widths

The DMC can support memory data bus widths of 16-bit, 32-bit, or 64-bit. However, during configuration of the DMC then it might not permit all of these options depending on the:

Configured AXI data bus width.
Type of memory device, SDR or DDR, that the DMC controls. When the DMC controls:
SDR devices
The memory data bus width must not be less than half of the AXI data bus width.
DDR devices
The memory data bus width must not be less than one quarter of the AXI data bus width, and no greater than the AXI data bus width.

Table 1.1 shows the memory device widths that you can connect to a DMC depending on the configured AXI bus width and configured memory data bus width, MEMWIDTH.

Table 1.1. Supported memory device types for different DMC configurations

AXI data bus width	Memory interface data bus width, MEMWIDTH	SDR device width	DDR device width
32-bit	16-bit	16-bit	16-bit
	32-bit	32-bit 16-bit ^[a]	32-bit 16-bit ^[a]
	64-bit	-	-
64-bit	16-bit	-	16-bit
	32-bit	32-bit -	32-bit 16-bit ^[a]
	64-bit	-	64-bit 32-bit ^[a]
128-bit	16-bit	-	-
	32-bit	- -	32-bit
	64-bit	-	64-bit 32-bit ^[a]
^[a]To use devices of this data width you must disable the DMC from using the upper half of the data bus on the memory interface by setting the memory_width[1:0] tie-off or programming the memory_width field in the Memory Configuration 2 Register.

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