3.3.22. Update Type Register

The update_type Register characteristics are:

Purpose

Controls how the DMC responds when it receives any of the four possible update type requests from a PHY device.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available when the DMC is configured to support a DFI pad interface.

Attributes

See the register summary in Table 3.1.

Figure 3.28 shows the update_type Register bit assignments.

Figure 3.28. update_type Register bit assignments


Table 3.25 shows the update_type Register bit assignments.

Table 3.25. update_type Register bit assignments

BitsNameFunction
[31:8]-Read undefined, write as zero.
[7:6]phyupd_type_11

Controls how the DMC responds to a DFI update request type 3, that is, when the PHY sets dfi_phyupd_type[1:0] to b11:

b00 = Put the memory devices in self-refresh mode then stall the DFI

b01 = Stall the DFI

b10-b11 = Reserved.

[5:4]phyupd_type_10

Controls how the DMC responds to a DFI update request type 2, that is, when the PHY sets dfi_phyupd_type[1:0] to b10:

b00 = Put the memory devices in self-refresh mode then stall the DFI

b01 = Stall the DFI

b10-b11 = Reserved.

[3:2]phyupd_type_01

Controls how the DMC responds to a DFI update request type 1, that is, when the PHY sets dfi_phyupd_type[1:0] to b01:

b00 = Put the memory devices in self-refresh mode then stall the DFI

b01 = Stall the DFI

b10-b11 = Reserved.

[1:0]phyupd_type_00

Controls how the DMC responds to a DFI update request type 0, that is, when the PHY sets dfi_phyupd_type[1:0] to b00:

b00 = Put the memory devices in self-refresh mode then stall the DFI

b01 = Stall the DFI

b10-b11 = Reserved.


Copyright © 2004-2007, 2009 ARM Limited. All rights reserved.ARM DDI 0331G
Non-Confidential