3.3.23. Read Data Enable Timing Register

The t_rddata_en Register characteristics are:

Purpose

Controls the trddata_en timing parameter on the DFI pad interface.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available when the DMC is configured to support a DFI pad interface.

Attributes

See the register summary in Table 3.1.

Figure 3.29 shows the t_rddata_en Register bit assignments.

Figure 3.29. t_rddata_en Register bit assignments


Table 3.26 shows the t_rddata_en Register bit assignments.

Table 3.26. t_rddata_en Register bit assignments

BitsNameFunction
[31:4]-Read undefined, write as zero.

[3:0]

t_rddata_en

After a DMC issues a Read command from the DFI pad interface then this field sets the number of mclk cycles before dfi_rddata_en[MEMORY_BYTES-1:0] goes HIGH.

The valid values for this field depend on the cas_latency setting and the limits are:

Minimum

cas_latency- 1

Maximum

cas_latency+ 6

For example, if cas_latency = 3, then set this field to any value between b0010 and b1001.


Copyright © 2004-2007, 2009 ARM Limited. All rights reserved.ARM DDI 0331G
Non-Confidential