AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual: Appendix B. Revisions

Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Differences between issue F and issue G

Change	Location	Affects
Added the DDR PHY Interface (DFI) pad interface feature including the DFI signals and registers	Throughout book	r4p0
Updated description of the supported memory data bus widths	Supported memory widths	All revisions
Removed support for 64-bit SDRAMs	Table 1.1	r4p0
Updated AXI slave interface attributes and added read interleave depth	AXI slave interface attributes	All revisions
Updated bus widths for arprot, awprot, arcache, and awcache	Figure 2.2 AXI signals	All revisions
Added user_config1 signals and user_config1 Register	Miscellaneous signals User Config1 Register User signals	r4p0
Added configurable bus width for the user_status, user_config, and user_config1 signals	Throughout book	r4p0
Added configurable bus width for the arid, awid, bid, rid, and wid signals	Throughout book	r4p0
Added early write response feature	Early BRESP	r4p0
Added Read After Write hazard	Hazard detection	r4p0
Updated description of system state 11	Table 2.6	All revisions
Updated listing of the dynamic low-power modes operation and removed the illegal bit combinations	Table 2.7	All revisions
Removed restriction of issuing the NOP command when the controller includes the NVM plug-in	Controller management operations Deep Power-Down Table 3.6	r4p0
Support for moving all of the memory devices to the deep power-down mode	Deep Power-Down	r4p0
Added a new section TrustZone Support for DMC	TrustZone technology support	r4p0
Added supported bit, or field, values to the timing registers	Chapter 3 Programmers Model	All revisions
Updated the function description for fp_time bit	Table 3.7	r4p0
Field names changed as follows: from memory_banks[1:0] to banks_bit[1:0] from memory_type to memory_support from memory_width to max_memory_width	Memory Controller Status Register	r2p0
Added the combined SDR-DDR-LPDDR option to the memory_support field		r2p0
Updated description of the max_memory_width field		All revisions
Updated description of the sr_enable, fp_time, and fp_enable bits	Memory Configuration Register	All revisions
Removed restriction of enabling the sr_enable and stop_mem_clock bits at the same time	Memory Configuration Register	r4p0
Updated description of the cas_half_cycle bit	CAS Latency Register	All revisions
Updated description of the memory_width field	Memory Configuration 2 Register	r2p0
memory_type field name changed to memory_protocol
Added the combined SDR-DDR-LPDDR option to the memory_protocol field
a_gt_m_sync bit and sync bit changed to clock_cfg field
Updated description of the memory_cfg3 Register	Memory Configuration 3 Register	r2p0
Added the read_transfer_delay Register	Read Transfer Delay Register	r4p0
brc_n_rbc field name changed to address_fmt	Chip Configuration Register	r3p0
Added the feature_ctrl Register	Feature Control Register	r4p0
Updated the most significant byte of the conceptual peripheral ID register	Figure 3.37 Table 3.34	All revisions
Added requirement to set cactive and csysack HIGH when the controller exits integration test mode	Integration Configuration Register	All revisions
Updated register description and added an _int suffix to each bit name	Integration Outputs Register	All revisions
Replaced the old Device Driver section with new content	Chapter 5 Device Driver	r4p0
Updated description of the tie-off signals	Tie-offs	All revisions
Added note about using EBI when DFI is implemented	EBI signals	r4p0

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