2.2.9. Memory interface

The memory interface is separated from the arbiter using the following configurable synchronous or asynchronous FIFOs and buffer:

Note

Synchronous relates to rising edge-aligned clocks.

The memory interface reads commands from the arbiter using the command FIFO but only when that command can be executed. The memory interface ensures a command is only executed when all the inter-command delays, defined in this section, for that bank or memory device are met.

The memory interface enables multiple banks to be active at any one time. However, only one bank can be carrying out a data transfer at any one time. If the command at the head of the command FIFO cannot be executed, then the command pipeline stalls until it can be executed.

Scheduler

To reduce the occurrence of pipeline stalls, the DMC contains a scheduler that monitors the activity of the mclk FSMs in the memory interface. The scheduler uses the information in the schedule fields of the t_rcd, t_rfc and t_rp registers, to prevent the arbiter from issuing commands that can stall the command pipeline. Program the schedule fields with the amount of delay you require, in aclk cycles. For synchronized 1:1 operation of aclk and mclk, program:

For non-synchronized 1:1 operation, you must scale the schedule_rx fields accordingly.

Note

For the LPDDR NVM add-on, the nvm_schedule_rcd is applied when accessing NVM chips.

Memory interface to pad interface timing

All command control outputs are clocked on the falling edge of the memory clock, mclk. The relative times between control signals from the memory interface are maintained when output from the pad interface to the actual SDRAM devices. Therefore, the timing register values required for a particular SDRAM device can be determined from that SDRAM device’s data sheet.

Figure 2.13 to Figure 2.24 show how the data sheet timings map on to the DMC timing registers. Figure 3.2 shows the timing registers.

Note

In Figure 2.13 to Figure 2.24:

  • The following signals are internal to the DMC:

    • command_en

    • data_cntl_en

    • memif_busy

    • pwr_down

    • read_en.

  • The timings shown are not necessarily the default timing values but are values that are small enough to show the entire delay in one figure.

Figure 2.13 shows the command control output timing.

Figure 2.13. Command control output timing


Figure 2.14 shows the ACTIVE command to Read or Write command timing, that you program using the ACTIVE to Read or Write Timing Register.

Figure 2.14. ACTIVE command to Read or Write command timing, tRCD


Figure 2.15 shows ACTIVE to ACTIVE on the same bank, and ACTIVE to AUTO REFRESH command timing, that you program using the ACTIVE to ACTIVE Timing Register.

Figure 2.15. Same bank ACTIVE to ACTIVE, and ACTIVE to AUTO REFRESH command timing, tRC


Figure 2.16 shows the ACTIVE to ACTIVE command timing to different memory banks, that you program using the ACTIVE to ACTIVE Different Bank Timing Register.

Figure 2.16. Different bank ACTIVE to ACTIVE command timing, tRRD


Figure 2.17 shows the PRECHARGE to command, and AUTO REFRESH timing, that you program using the PRECHARGE to Command Timing Register and AUTO REFRESH to Command Timing Register.

Figure 2.17. PRECHARGE to command and AUTO REFRESH to command timing, tRP and tRFC


Figure 2.18 shows ACTIVE to PRECHARGE, and PRECHARGE to PRECHARGE timing, that you program using the ACTIVE to PRECHARGE Timing Register and PRECHARGE to Command Timing Register.

Figure 2.18. ACTIVE to PRECHARGE, and PRECHARGE to PRECHARGE timing, tRAS and tRP


Figure 2.19 shows MODEREG to command timing, that you program using the MODEREG to Command Timing Register.

Figure 2.19. MODEREG to command timing, tMRD


Figure 2.20 shows self-refresh entry and exit timing, that you program using the Self-refresh to Command Timing Register and Exit Self-refresh Timing Register.

Figure 2.20. Self-refresh entry and exit timing, tESR and tXSR


Figure 2.21 shows power-down entry and exit timing, that you program using the Memory Configuration 3 Register and Exit Power-down Timing Register.

Figure 2.21. Power-down entry and exit timing, tXP


The power_dwn_prd count is timed from the memory interface becoming idle, that is, after a command delay has timed out or the read data FIFO is emptied. cke is asserted when the command FIFO is not empty.

Figure 2.22 shows the turnaround time, tWTR, for the memory interface to output a Write command followed immediately by a Read command. Program this value using the Write to Read Timing Register.

Figure 2.22. Data output timing, tWTR


Figure 2.23 shows the relationship between the memory interface outputting a Write command and the write data, when tDQSS is set to 1 using the Write to DQS Timing Register. It also highlights the tWR minimum time between a Write and a PRECHARGE command, that you program using the Write to PRECHARGE Timing Register.

Figure 2.23. Data output timing, tDQSS = 1


Figure 2.24 shows the timing relationship between the Read command being output from the memory interface and the read data being returned to the memory interface from the pad interface. Program this timing using the CAS Latency Register and the read_delay field in the Memory Configuration 2 Register.

Figure 2.24. Data input timing


Note

The SDR configuration requires read_delay set to zero.

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