AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.16. Write to Read Timing Register

The t_wtr Register characteristics are:

Purpose

Controls the Write to Read delay in memory clock cycles, see Figure 2.22.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.22 shows the t_wtr Register bit assignments.

Figure 3.22. t_wtr Register bit assignments


Table 3.19 shows the t_wtr Register bit assignments.

Table 3.19. t_wtr Register bit assignments

Bits

Name

Function

[31:3]-Read undefined, write as zero.
[2:0]t_wtrSets tWTR, the Write to Read command delay in memory clock cycles. Supported values are 1-7.

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