AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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A.3.3. Write response channel signals

Table A.8 shows the AXI write response channel signals.

Table A.8. Write response channel signals

Signal AMBA equivalent [a]
bid[AID_WIDTH-1:0] [b]BID[AID_WIDTH-1:0]
breadyBREADY
bresp[1:0] [c]BRESP[1:0]
bvalidBVALID

[a] For a description of these signals, see the AMBA AXI Protocol v1.0 Specification.

[b] The value of AID_WIDTH is set during configuration of the DMC.

[c] The DMC ties bresp[1] LOW and therefore it only provides OKAY or EXOKAY responses.


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