3.3.2. Memory Controller Command Register

The memc_cmd Register characteristics are:

Purpose

Controls the operating state of the DMC.

Usage constraints

Not accessible in the Reset or Power-On Reset (POR) state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.8 shows the memc_cmd Register bit assignments.

Figure 3.8. memc_cmd Register bit assignments


Table 3.4 shows the memc_cmd Register bit assignments.

Table 3.4. memc_cmd Register bit assignments

Bits

Name

Function

[31:3]-Undefined, write as zero.

[2:0]

memc_cmd

Use the following commands to change the state of the DMC:

b000 = Go

b001 = Sleep

b010 = Wakeup

b011 = Pause

b100 = Configure

b111 = Active_Pause.

If the controller receives a command to change state and a previous command to change state has not completed then it holds pready LOW until the new command can be carried out.

For more information about the state transitions, see Figure 2.12.


Note

  • Active_Pause command puts the DMC into the Paused state without draining the arbiter queue. This enables you to move the controller to the Low_power state, to change configuration settings such as memory frequency or timing register values, without requiring coordination between masters in a multi-master system.

  • If you use the Active_Pause command to put the DMC in the Low_power state then you must not remove power from the DMC because this results in data loss and violation of the AXI protocol.

  • The DMC does not issue refreshes when in the Config state. Therefore, ARM recommends that you make register updates with the controller in Low_power state because this ensures that the memory is put into self-refresh mode, rather than the Config state when the memory contains valid data.

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