AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.13. PRECHARGE to Command Timing Register

The t_rp Register characteristics are:

Purpose

Controls the PRECHARGE to RAS delay in memory clock cycles, see Figure 2.17 and Figure 2.18.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.19 shows the t_rp Register bit assignments.

Figure 3.19. t_rp Register bit assignments


Table 3.16 shows the t_rp Register bit assignments.

Table 3.16. t_rp Register bit assignments

Bits

Name

Function

[31:6]-Read undefined, write as zero.
[5:3]schedule_rpSets the PRECHARGE to RAS delay in aclk cycles minus 3. Supported values are 0-7. For more information, see Scheduler.
[2:0]t_rpSets tRP, the PRECHARGE to RAS delay in memory clock cycles. Supported values are 1-7.

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