3.3.26. Chip Configuration Register

The chip_cfg<n> Register characteristics are:

Purpose

Each register sets the:

  • address decode for chip select <n>

  • bank, row, column organization of the memory device that connects to chip select <n>.

Usage constraints
  • Only accessible in Config or Low_power state.

  • The number of registers implemented is equal to the number of chip selects that a configured controller supports.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.32 shows the chip_cfg<n> Register bit assignments.

Figure 3.32. chip_cfg<n> registers bit assignments


Table 3.29 shows the chip_cfg<n> Register bit assignments.

Table 3.29. chip_cfg<n> registers bit assignments

BitsNameFunction
[31:17]-Read undefined, write as zero.

[16]

address_fmt<n>

Selects the memory organization as decoded from the AXI address:

0 = Row, Bank, Column (RBC) organization

1 = Bank, Row, Column (BRC) organization.

[15:8]address_match<n>The controller applies the address_mask<n> field to the AXI address bits, [31:24], that is awaddr[31:24] or araddr[31:24]. The controller compares the result against this field and if a match occurs then it selects memory device <n>. See Formatting from AXI address channels.

[7:0]

address_mask<n>

Controls which AXI address bits, [31:24], the DMC compares when it receives an AXI transfer:

Bit [x] = 0

DMC excludes AXI address bit [24+x] from the comparison

Bit [x] = 1

DMC includes AXI address bit [24+x] in the comparison.


Note

If a configured controller supports two or more memory devices then you must take care to ensure that for all AXI addresses, you program the various address_match and address_mask fields so that the controller can only assert a single memory chip select. Otherwise, Unpredictable behavior might occur.

Copyright © 2004-2007, 2009 ARM Limited. All rights reserved.ARM DDI 0331G
Non-Confidential