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Table A.10 shows the AXI read data channel signals.
Table A.10. Read data channel signals
| Signal | AMBA equivalent [a] |
|---|---|
| rdata[AXI_DATA_MSB:0] [b] | RDATA |
| rid[AID_WIDTH-1:0] [b] | RID[AID_WIDTH-1:0] |
| rlast | RLAST |
| rready [c] | RREADY |
| rresp[1:0] [d] | RRESP[1:0] |
| rvalid | RVALID |
[a] For a description of these signals, see the AMBA AXI Protocol v1.0 Specification. [b] The value of AXI_DATA_MSB and AID_WIDTH are set during configuration of the DMC. [c] It is possible for refreshes to be missed if rready is held LOW for longer than one refresh period, and the read data FIFO, command FIFO, and arbiter queue become full. An OVL error is triggered if this occurs in simulation. Ensure that the device has a sufficiently high system priority to prevent this. [d] The DMC ties rresp[1] LOW and therefore it only provides OKAY or EXOKAY responses. | |
| Copyright © 2004-2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0331G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > AXI signals > Read data channel signals |