3.3.11. ACTIVE to Read or Write Timing Register

The t_rcd Register characteristics are:

Purpose

Controls the delay between an ACTIVE command and another memory command, other than ACTIVE, to the same bank, see Figure 2.14.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.17 shows the t_rcd Register bit assignments.

Figure 3.17. t_rcd Register bit assignments


Table 3.14 shows the t_rcd Register bit assignments.

Table 3.14. t_rcd Register bit assignments

Bits

Name

Function

[31:6]-Read undefined, write as zero.
[5:3]schedule_rcdSets the RAS to CAS delay in aclk cycles minus 3. For more information, see Scheduler. Supported values are 0-7.
[2:0]t_rcdSets tRCD, the RAS to CAS delay in memory clock cycles. Supported values are 1-7.

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