AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.21. Memory Configuration 3 Register

The memory_cfg3 Register characteristics are:

Purpose

Controls the:

  • power_dwn_prd prescalar value

  • number of outstanding AUTO REFRESH commands.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.27 shows the memory_cfg3 Register bit assignments.

Figure 3.27. memory_cfg3 Register bit assignments


Table 3.24 shows the memory_cfg3 Register bit assignments.

Table 3.24. memory_cfg3 Register bit assignments

BitsNameFunction
[31:13]-Read undefined, write as zero.
[12:3]prescalePrescalar counter value. Supported values are 0-1023. See Auto self-refresh entry.
[2:0]max_outs_refsMaximum number of outstanding refresh commands. Supported values are 1-7. See QoS for AUTO REFRESH.

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