AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.10. ACTIVE to ACTIVE Timing Register

The t_rc Register characteristics are:

Purpose

Controls the ACTIVE bank x to ACTIVE bank x delay in memory clock cycles, see Figure 2.15.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.16 shows the t_rc Register bit assignments.

Figure 3.16. t_rc Register bit assignments


Table 3.13 shows the t_rc Register bit assignments.

Table 3.13. t_rc Register bit assignments

Bits

Name

Function

[31:4]-Read undefined, write as zero.
[3:0]t_rcSets tRC, the ACTIVE bank x to ACTIVE bank x delay in memory clock cycles. Supported values are 1-15.

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