AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.9. ACTIVE to PRECHARGE Timing Register

The t_ras Register characteristics are:

Purpose

Controls the ACTIVE to PRECHARGE delay in memory clock cycles, see Figure 2.18.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.15 shows the t_ras Register bit assignments.

Figure 3.15. t_ras Register bit assignments


Table 3.12 shows the t_ras Register bit assignments.

Table 3.12. t_ras Register bit assignments

Bits

Name

Function

[31:4]-Read undefined, write as zero.
[3:0]t_rasSets tRAS, the ACTIVE to PRECHARGE delay in memory clock cycles. Supported values are 1-15.

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