AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.18. Exit Self-refresh Timing Register

The t_xsr Register characteristics are:

Purpose

Controls the exit self-refresh to command delay in memory clock cycles, see Figure 2.20.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.24 shows the t_xsr Register bit assignments.

Figure 3.24. t_xsr Register bit assignments


Table 3.21 shows the t_xsr Register bit assignments.

Table 3.21. t_xsr Register bit assignments

Bits

Name

Function

[31:8]-Read undefined, write as zero.
[7:0]t_xsrSets tXSR, the exit self-refresh to command delay in memory clock cycles. Supported values are 1-255.

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