4.1.1. Integration Configuration Register

The int_cfg Register characteristics are:

Purpose

Controls the enabling of the integration test logic.

Usage constraints

Only accessible in Config state. ARM recommends that it is only accessed for integration testing or production testing.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 4.1.

Figure 4.2 shows the int_cfg Register bit assignments.

Figure 4.2. int_cfg Register bit assignments


Table 4.2 shows the int_cfg Register bit assignments.

Table 4.2. int_cfg Register bit assignments

BitsNameFunction
[31:1]-Read undefined, write as zero.

[0]

int_test_en

Enables the integration test logic:

0 = disables the integration test logic

1 = enables the integration test logic.

Note

When the controller exits integration test mode, the cactive and csysack signals must be HIGH, even if the SoC does not use these signals. To satisfy this requirement you must program the int_outputs Register, see Integration Outputs Register.


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