AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.5. Refresh Period Register

The refresh_prd Register characteristics are:

Purpose

Controls the memory refresh period in memory clock cycles.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.11 shows the refresh_prd Register bit assignments.

Figure 3.11. refresh_prd Register bit assignments


Table 3.8 shows the refresh_prd Register bit assignments.

Table 3.8. refresh_prd Register bit assignments

Bits

Name

Function

[31:15]-Read undefined, write as zero.
[14:0]refresh_prdMemory refresh period in memory clock cycles. Supported values are 0-32767.

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