AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual: 3.3.25. QoS Configuration Register

The id_<n>_cfg Register characteristics are:

Purpose: Sets the parameters for QoS <n>. Where <n> is a value from 0 to 15 and is the result of applying the 4-bit QoS mask to the arid[ ] bus.
Usage constraints: Only accessible in Config or Low_power state.
Configurations: Available in all configurations of the DMC.
Attributes: See the register summary in Table 3.1.

Figure 3.31 shows the id_<n>_cfg Register bit assignments.

Figure 3.31. id_<n>_cfg Register bit assignments

Table 3.28 shows the id_<n>_cfg Register bit assignments.

Table 3.28. id_<n>_cfg Register bit assignments

Bits	Name	Function
[31:10]	-	Read undefined, write as zero.
[9:2]	qos_max<n>	Sets the maximum QoS value. Supported values are 0-255.
[1]	qos_min<n>	Enables the minimum QoS functionality: 0 = disabled, so the arbiter entry uses the qos_max<n> value 1 = enabled. the arbiter entry uses minimum latency.
[0]	qos_enable<n>	When set, the DMC can apply QoS to a read transfer if the masking of the arid[ ] bits with the programmed QoS mask produces a value of <n>. For more information, see Quality of Service.

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