AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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3.3.12. AUTO REFRESH to Command Timing Register

The t_rfc Register characteristics are:

Purpose

Controls the AUTO REFRESH to command delay in memory clock cycles, see Figure 2.17.

Usage constraints

Only accessible in Config or Low_power state.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

Figure 3.18 shows the t_rfc Register bit assignments.

Figure 3.18. t_rfc Register bit assignments


Table 3.15 shows the t_rfc Register bit assignments.

Table 3.15. t_rfc Register bit assignments

Bits

Name

Function

[31:10]-Read undefined, write as zero.
[9:5]schedule_rfcSets the AUTO REFRESH to command delay in aclk cycles minus 3. Supported values are 0-31. For more information, see Scheduler.
[4:0]t_rfcSets tRFC, the AUTO REFRESH to command delay in memory clock cycles. Supported values are 1-31.

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