2.2.7. Controller management operations

The memory manager tracks and controls the current state of the DMC using the aclk Finite State Machine (FSM). You can change the state of the controller by programming the memc_cmd Register, see Memory Controller Command Register.

You can also use the AXI low-power interface to move the controller between the Ready and Low_power states, see System low-power control.

Figure 2.12 shows the aclk FSM.

Figure 2.12. aclk domain state diagram


In Figure 2.12 non-state moving transitions are omitted for clarity.

Note

  • If the DMC receives an APB command that is illegal to carry out from the current state then the DMC ignores it and the aclk FSM stays in the same state.

  • If the DMC moves to the Paused state using Active_Pause then it is not permitted to enter the Config state.

  • For the two cycles following Power-On-Reset (POR), do not consider the DMC to be in the Config state. For this reason, register access restrictions apply.

  • You can only use the AXI low-power interface to move in and out of the Low_power state from the Ready state.

  • If the DMC enters the Low_power state using the:

    • APB interface then it must also exit the Low_power state using the APB interface

    • AXI low-power interface then it must also exit the Low_power state using the AXI low-power interface.

The current status of the aclk FSM controls the functionality of the DMC:

Note

No AUTO REFRESH commands are generated when in the Config state. If you are changing register values, it is necessary to enter the Low_power state, because this removes the risk of the memory maximum refresh time being exceeded.

The DMC management function can issue commands to the memory interface from one of the following sources:

Direct commands

These are received over the APB interface as a result of a write to the direct_cmd Register. See Direct Command Register. They initialize the SDRAM.

The legal commands that the memory manager uses are:

  • NOP

  • PRECHARGEALL

  • AUTO REFRESH

  • MODEREG

  • extended MODEREG

  • Deep Power-Down (DPD).

Commands from the aclk FSM

You can traverse the aclk FSM by writing to the memc_cmd Register. See Memory Controller Command Register. You can only traverse the aclk FSM states when the DMC is idle. For example, the Ready state can only be entered from the Config state when all direct commands have been completed. The exception to this is the Active_Pause command. You can issue this command when the DMC is active. When you issue the command, any memory accesses that have not been arbitrated remain in the arbiter until the aclk FSM receives the Go command.

Refresh commands

The refresh logic can issue commands to the arbiter to refresh the SDRAM chips. The refresh counter is clocked by the memory clock to enable the frequency of the DMC to be scaled without affecting the refresh rate. The refresh rate period is programmable using the refresh_prd Register. See Refresh Period Register. The value of this register is the count value in mclk cycles.

When the refresh counter wraps around zero, an individual auto-refresh sequence is requested for each external chip in turn.

You can prevent Refresh commands from being generated by using the active_chips field in the memory_cfg Register. See Memory Configuration Register.

Note

Refreshes are masked from the most significant chip number downwards.

These management commands are arbitrated with data commands.

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