2.1.6. Memory interface

The memory interface provides a clean and defined interface between the arbiter and the pad interface, ensuring that the external memory interface command protocols are met in accordance with the programmed timings in the register block. See Chapter 3 Programmers Model.

The external inputs and outputs to this block are:


Clock for mclk domain.


Reset for mclk domain. This signal is active LOW.


Tie this LOW to indicate that the DMC must not back off from the bus, if you are not using an External Bus Interface (EBI).


Tie this HIGH to indicate that the bus is always granted, if you are not using an EBI.


Leave this unconnected, if you are not using an EBI.


Tie this LOW, if you are not using an EBI.

The memory interface tracks and controls the state of the external memories using either an mclk Finite State Machine (FSM) per extended memory or one mclk FSM depending on the configuration of the DMC. Figure 2.7 shows an mclk domain FSM.

Figure 2.7. mclk domain FSM

See Table 2.5 for valid system states and Deep Power-Down.

For more information, see Memory interface.

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