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Table A.7 shows the AXI write data channel signals.
Table A.7. Write data channel signals
| Signal | AMBA equivalent [a] |
|---|---|
| wdata[AXI_DATA_MSB:0] [b] | WDATA |
| wid[AID_WIDTH-1:0] [b] | WID[AID_WIDTH-1:0] |
| wlast | WLAST |
| wready | WREADY |
| wstrb[AXI_STRB_MSB:0] [b] | WSTRB |
| wvalid | WVALID |
[a] For a description of these signals, see the AMBA AXI Protocol v1.0 Specification. [b] The value of AXI_DATA_MSB and AID_WIDTH are set during configuration of the DMC. AXI_STRB_MSB = AXI_DATA_MSB ÷ 8. | |
| Copyright © 2004-2007, 2009 ARM Limited. All rights reserved. | ARM DDI 0331G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > AXI signals > Write data channel signals |