3.2. Register summary

Table 3.1 shows the DMC registers in base offset order.

Table 3.1. DMC register summary

OffsetNameTypeResetDescription
0x000memc_statusRO- [a]Memory Controller Status Register
0x004memc_cmdWO-Memory Controller Command Register
0x008direct_cmdWO-Direct Command Register
0x00Cmemory_cfgRW0x00010020Memory Configuration Register
0x010refresh_prdRW0x00000A60Refresh Period Register
0x014cas_latencyRW0x00000006CAS Latency Register
0x018t_dqssRW0x00000001Write to DQS Timing Register
0x01Ct_mrdRW0x00000002MODEREG to Command Timing Register
0x020t_rasRW0x00000007ACTIVE to PRECHARGE Timing Register
0x024t_rcRW0x0000000BACTIVE to ACTIVE Timing Register
0x028t_rcdRW0x0000001DACTIVE to Read or Write Timing Register
0x02Ct_rfcRW0x00000212AUTO REFRESH to Command Timing Register
0x030t_rpRW0x0000001DPRECHARGE to Command Timing Register
0x034t_rrdRW0x00000002ACTIVE to ACTIVE Different Bank Timing Register
0x038t_wrRW0x00000003Write to PRECHARGE Timing Register
0x03Ct_wtrRW0x00000002Write to Read Timing Register
0x040t_xpRW0x00000001Exit Power-down Timing Register
0x044t_xsrRW0x0000000AExit Self-refresh Timing Register
0x048t_esrRW0x00000014Self-refresh to Command Timing Register
0x04Cmemory_cfg2RW- [b]Memory Configuration 2 Register
0x050memory_cfg3RW0x00000007Memory Configuration 3 Register
0x054---Reserved, read undefined, write as zero
0x058update_type [c]RW0x00000000Update Type Register
0x05Ct_rddata_en [c]RW0x00000000Read Data Enable Timing Register
0x060 - 0x078---Reserved, read undefined, write as zero
0x07Cread_transfer_delayRW0x00000001Read Transfer Delay Register
0x080 - 0x0FC---Reserved, read undefined, write as zero
0x100 - 0x13Cid_<n>_cfgRW0x00000000QoS Configuration Register
0x140 - 0x1FC---Reserved, read undefined, write as zero

0x200

0x204 [d]

0x208 [d]

0x20C [d]

chip_cfg0

chip_cfg1

chip_cfg2

chip_cfg3

RW

0x0000FF00

Chip Configuration Register

0x210 - 0x2FC---Reserved, read undefined, write as zero
0x300user_statusRO-User Status Register
0x304user_configWO-User Config Register
0x308user_config1WO-User Config1 Register
0x30Cfeature_ctrlRW0x00000001Feature Control Register
0x310 - 0xDFC---Reserved, read undefined, write as zero

0xE00

0xE04

0xE08

int_cfg

int_inputs

int_outputs

For more information about these registers, see Chapter 4 Programmers Model for Test.
0xE0C - 0xFDC---Reserved, read undefined, write as zero
0xFE0 - 0xFECperiph_id_nRO0x00_41340 [e]Peripheral Identification Register
0xFF0 - 0xFFCpcell_id_nRO0xB105F00DComponent identification registers

[a] Dependent on configuration.

[b] Dependent on tie-off signal values.

[c] This register is only present when the DMC is configured to implement a DDR PHY Interface (DFI), otherwise reads are undefined, write as zero.

[d] The presence of this register depends on the number of chip selects that a configured controller supports. If a controller does not implement the register then reads are undefined, write as zero.

[e] Dependent on the revision of the DMC, see Peripheral Identification Register 2.


Copyright © 2004-2007, 2009 ARM Limited. All rights reserved.ARM DDI 0331G
Non-Confidential