AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference ManualRevision: r4p0
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2.1. Functional overview

Figure 2.1 shows the interfaces of the DMC.

Figure 2.1. DMC block diagram


Note

If the DMC is configured to support a DDR PHY Interface (DFI) pad interface, then the EBI signals are not available.

The interfaces of the DMC are:

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