3.3.31. Peripheral Identification Register

The periph_id_[3:0] Register characteristics are:

Purpose

Provide information about the configuration and version of the peripheral.

Usage constraints

No usage constraints.

Configurations

Available in all configurations of the DMC.

Attributes

See the register summary in Table 3.1.

These registers can conceptually be treated as a single register that holds a 32-bit peripheral ID value. Figure 3.37 shows the correspondence between bits [7:0] of the periph_id registers and the conceptual 32-bit Peripheral ID Register.

Figure 3.37. periph_id_[3:0] Register bit assignments


Table 3.34 shows the register bit assignments for the conceptual 32-bit peripheral ID Register.

Table 3.34. Conceptual peripheral ID Register bit assignments

BitsNameFunction
[31:28]-Reserved.
[27:24]customer modifiedIdentifies data that is relevant to an ARM partner.
[23:20]revisionIdentifies the RTL revision of the peripheral.
[19:12]designerIdentifies the designer. This is 0x41 for ARM.
[11:0]part_numberIdentifies the peripheral. The part number for the DMC is 0x340.

The periph_id registers are described in:

Peripheral Identification Register 0

The periph_id_0 Register is hard-coded and the fields in the register control the reset value. Table 3.35 shows the register bit assignments.

Table 3.35. periph_id_0 Register bit assignments

BitsNameFunction
[31:8]-Read undefined
[7:0]part_number_0Returns 0x40

Peripheral Identification Register 1

The periph_id_1 Register is hard-coded and the fields in the register control the reset value. Table 3.36 shows the register bit assignments.

Table 3.36. periph_id_1 Register bit assignments

BitsNameFunction
[31:8]-Read undefined
[7:4]designer_0Returns 0x1
[3:0]part_number_1Returns 0x3

Peripheral Identification Register 2

The periph_id_2 Register is hard-coded and the fields in the register control the reset value. Table 3.37 shows the register bit assignments.

Table 3.37. periph_id_2 Register bit assignments

BitsNameFunction
[31:8]-Read undefined

[7:4]

revision

These bits return the revision number:

  • 0x0 is r0p0

  • 0x1 is r1p0

  • 0x2 is r2p0

  • 0x3 is r3p0

  • 0x4 is r4p0

[3:0]designer_1Returns 0x4

Peripheral identification Register 3

The periph_id_3 Register is hard-coded and the fields in the register control the reset value. Table 3.38 shows the register bit assignments.

Table 3.38. periph_id_3 Register bit assignments

BitsNameFunction
[31:8]-Read undefined
[7:4]-Reserved for future use, read undefined
[3:0]customer modifiedCustomer modified number, 0x0 from ARM

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