AMBA DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual: 3.3.32. Component identification registers

3.3.32. Component identification registers

The pcell_id_[3:0] Register characteristics are:

Purpose: When concatenated, these four registers return 0xB105F00D
Usage constraints: No usage constraints.
Configurations: Available in all configurations of the DMC.
Attributes: See the register summary in Table 3.1.

These registers can be treated conceptually as a single register that holds a 32-bit Component identification value. You can use the register for automatic BIOS configuration.

Figure 3.38 shows the register bit assignments.

Figure 3.38. pcell_id Register bit assignments

Table 3.39 shows the register bit assignments.

Table 3.39. pcell_id Register bit assignments

pcell_id Register		pcell_id_[3:0] registers
Bits	Reset value	Register	Bits	Description
[31:24]	`0xB1`	pcell_id_3	[31:8]	Read undefined
[31:24]	`0xB1`	pcell_id_3	[7:0]	Returns `0xB1`
[23:16]	`0x05`	pcell_id_2	[31:8]	Read undefined
[23:16]	`0x05`	pcell_id_2	[7:0]	Returns `0x05`
[15:8]	`0xF0`	pcell_id_1	[31:8]	Read undefined
[15:8]	`0xF0`	pcell_id_1	[7:0]	Returns `0xF0`
[7:0]	`0x0D`	pcell_id_0	[31:8]	Read undefined
[7:0]	`0x0D`	pcell_id_0	[7:0]	Returns `0x0D`

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