3.1.1. Register map

The register map of the DMC spans a 4KB region, see Figure 3.1.

Figure 3.1. Register map


In Figure 3.1 the register map consists of the following main blocks:

DMC configuration

Figure 3.2 shows the DMC configuration register map.

Figure 3.2. DMC configuration register map


AXI ID configuration

Figure 3.3 shows the AXI ID configuration register map.

Figure 3.3. AXI ID configuration register map


Chip configuration

Figure 3.4 shows the chip configuration register map.

Figure 3.4. Chip configuration register map


User configuration and Feature Control Register

Figure 3.5 shows the memory map for the Feature Control Register and the following user signals:

  • user_config1[ ]

  • user_config0[ ]

  • user_status[ ].

Figure 3.5. User configuration register map


Integration test

Use these registers to verify correct integration of the DMC within a system, by enabling non-AMBA signals to be set and read.

Component configuration

Figure 3.6 shows the Component configuration register map.

Figure 3.6. Component configuration register map


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