AMBA® DDR, LPDDR, and SDR Dynamic Memory Controller DMC-340 Technical Reference Manual

Revision: r4p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the DMC
1.1.1. Features of the DMC
1.1.2. Supported memory widths
1.1.3. Supported memory devices
1.2. Product revisions
2. Functional Description
2.1. Functional overview
2.1.1. AXI slave interface
2.1.2. AXI low-power interface
2.1.3. APB slave interface
2.1.4. Tie-off signals
2.1.5. User signals
2.1.6. Memory interface
2.1.7. Pad interface
2.1.8. QoS signal
2.1.9. EBI
2.2. Functional operation
2.2.1. Clocking and resets
2.2.2. AXI slave interface
2.2.3. AXI low-power interface
2.2.4. APB slave interface
2.2.5. Tie-off signals
2.2.6. Miscellaneous signals
2.2.7. Controller management operations
2.2.8. Data operations
2.2.9. Memory interface
2.2.10. Pad interface
2.2.11. Initialization
2.2.12. Low-power operation
2.2.13. TrustZone technology support
3. Programmers Model
3.1. About the programmers model
3.1.1. Register map
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Controller Command Register
3.3.3. Direct Command Register
3.3.4. Memory Configuration Register
3.3.5. Refresh Period Register
3.3.6. CAS Latency Register
3.3.7. Write to DQS Timing Register
3.3.8. MODEREG to Command Timing Register
3.3.9. ACTIVE to PRECHARGE Timing Register
3.3.10. ACTIVE to ACTIVE Timing Register
3.3.11. ACTIVE to Read or Write Timing Register
3.3.12. AUTO REFRESH to Command Timing Register
3.3.13. PRECHARGE to Command Timing Register
3.3.14. ACTIVE to ACTIVE Different Bank Timing Register
3.3.15. Write to PRECHARGE Timing Register
3.3.16. Write to Read Timing Register
3.3.17. Exit Power-down Timing Register
3.3.18. Exit Self-refresh Timing Register
3.3.19. Self-refresh to Command Timing Register
3.3.20. Memory Configuration 2 Register
3.3.21. Memory Configuration 3 Register
3.3.22. Update Type Register
3.3.23. Read Data Enable Timing Register
3.3.24. Read Transfer Delay Register
3.3.25. QoS Configuration Register
3.3.26. Chip Configuration Register
3.3.27. User Status Register
3.3.28. User Config Register
3.3.29. User Config1 Register
3.3.30. Feature Control Register
3.3.31. Peripheral Identification Register
3.3.32. Component identification registers
4. Programmers Model for Test
4.1. Integration test registers
4.1.1. Integration Configuration Register
4.1.2. Integration Inputs Register
4.1.3. Integration Outputs Register
5. Device Driver
5.1. Sample device driver
5.1.1. Memory controller initialization
5.1.2. Memory device initialization
5.1.3. Memory state control and status
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.2.1. QoS
A.2.2. Tie-offs
A.2.3. User signals
A.2.4. Scan test
A.3. AXI signals
A.3.1. Write address channel signals
A.3.2. Write data channel signals
A.3.3. Write response channel signals
A.3.4. Read address channel signals
A.3.5. Read data channel signals
A.3.6. AXI low-power interface signals
A.4. APB signals
A.5. Pad interface signals
A.5.1. Legacy pad interface
A.5.2. DFI pad interface
A.6. EBI signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example system
2.1. DMC block diagram
2.2. AXI slave interface connections
2.3. AXI low-power interface channel signals
2.4. APB signals
2.5. Tie-off signals
2.6. User signals
2.7. mclk domain FSM
2.8. Legacy pad interface signals
2.9. DFI pad interface signals
2.10. QoS signal
2.11. EBI signals
2.12. aclk domain state diagram
2.13. Command control output timing
2.14. ACTIVE command to Read or Write command timing, tRCD
2.15. Same bank ACTIVE to ACTIVE, and ACTIVE to AUTO REFRESH command timing, tRC
2.16. Different bank ACTIVE to ACTIVE command timing, tRRD
2.17. PRECHARGE to command and AUTO REFRESH to command timing, tRP and tRFC
2.19. MODEREG to command timing, tMRD
2.20. Self-refresh entry and exit timing, tESR and tXSR
2.21. Power-down entry and exit timing, tXP
2.22. Data output timing, tWTR
2.23. Data output timing, tDQSS = 1
2.24. Data input timing
2.25. System state transitions
2.26. Auto power-down
2.27. Force precharge with zero force precharge time
2.28. Force precharge after power_dwn_prd time
2.29. Auto self-refresh entry
2.30. DMC in context
3.1. Register map
3.2. DMC configuration register map
3.3. AXI ID configuration register map
3.4. Chip configuration register map
3.5. User configuration register map
3.6. Component configuration register map
3.7. memc_status Register bit assignments
3.8. memc_cmd Register bit assignments
3.9. direct_cmd Register bit assignments
3.10. memory_cfg Register bit assignments
3.11. refresh_prd Register bit assignments
3.12. cas_latency Register bit assignments
3.13. t_dqss Register bit assignments
3.14. t_mrd Register bit assignments
3.15. t_ras Register bit assignments
3.16. t_rc Register bit assignments
3.17. t_rcd Register bit assignments
3.18. t_rfc Register bit assignments
3.19. t_rp Register bit assignments
3.20. t_rrd Register bit assignments
3.21. t_wr Register bit assignments
3.22. t_wtr Register bit assignments
3.23. t_xp Register bit assignments
3.24. t_xsr Register bit assignments
3.25. t_esr Register bit assignments
3.26. memory_cfg2 Register bit assignments
3.27. memory_cfg3 Register bit assignments
3.28. update_type Register bit assignments
3.29. t_rddata_en Register bit assignments
3.30. read_transfer_delay Register bit assignments
3.31. id_<n>_cfg Register bit assignments
3.32. chip_cfg<n> registers bit assignments
3.33. user_status Register bit assignments
3.34. user_config Register bit assignments
3.35. user_config1 Register bit assignments
3.36. feature_ctrl Register bit assignments
3.37. periph_id_[3:0] Register bit assignments
3.38. pcell_id Register bit assignments
4.1. Integration test register map
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments

List of Tables

1.1. Supported memory device types for different DMC configurations
2.1. AXI slave interface attributes
2.2. Address comparison steps example
2.3. Controller initialization example
2.4. LPDDR device initialization example
2.5. Valid system states for the FSMs
2.6. Recommended power states
2.7. Dynamic low-power modes operation
3.1. DMC register summary
3.2. memc_status Register bit assignments
3.3. Memory banks chip configuration
3.4. memc_cmd Register bit assignments
3.5. direct_cmd Register bit assignments
3.6. Memory command encoding
3.7. memory_cfg Register bit assignments
3.8. refresh_prd Register bit assignments
3.9. cas_latency Register bit assignments
3.10. t_dqss Register bit assignments
3.11. t_mrd Register bit assignments
3.12. t_ras Register bit assignments
3.13. t_rc Register bit assignments
3.14. t_rcd Register bit assignments
3.15. t_rfc Register bit assignments
3.16. t_rp Register bit assignments
3.17. t_rrd Register bit assignments
3.18. t_wr Register bit assignments
3.19. t_wtr Register bit assignments
3.20. t_xp Register bit assignments
3.21. t_xsr Register bit assignments
3.22. t_esr Register bit assignments
3.23. memory_cfg2 Register bit assignments
3.24. memory_cfg3 Register bit assignments
3.25. update_type Register bit assignments
3.26. t_rddata_en Register bit assignments
3.27. read_transfer_delay Register bit assignments
3.28. id_<n>_cfg Register bit assignments
3.29. chip_cfg<n> registers bit assignments
3.30. user_status Register bit assignments
3.31. user_config Register bit assignments
3.32. user_config1 Register bit assignments
3.33. feature_ctrl Register bit assignments
3.34. Conceptual peripheral ID Register bit assignments
3.35. periph_id_0 Register bit assignments
3.36. periph_id_1 Register bit assignments
3.37. periph_id_2 Register bit assignments
3.38. periph_id_3 Register bit assignments
3.39. pcell_id Register bit assignments
4.1. DMC test Register summary
4.2. int_cfg Register bit assignments
4.3. int_inputs Register bit assignments
4.4. int_outputs Register bit assignments
A.1. Clock and reset signals
A.2. QoS signal
A.3. Tie-off signals
A.4. User signals
A.5. Scan test signals
A.6. Write address channel signals
A.7. Write data channel signals
A.8. Write response channel signals
A.9. Read address channel signals
A.10. Read data channel signals
A.11. AXI low-power interface signals
A.12. APB interface signals
A.13. Legacy pad interface signals
A.14. DFI pad interface signals
A.15. EBI signals
B.1. Differences between issue F and issue G

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A22 June 2004First release for r0p0.
Revision B31 August 2004Second release for r0p0.
Revision C25 August 2005Incorporate erratum. Additional information to Exclusive access on page 2-14.
Revision D09 June 2006First release for r1p0.
Revision E16 May 2007First release for r2p0.
Revision F30 November 2007First release for r3p0.
Revision G05 November 2009First release for r4p0.
Copyright © 2004-2007, 2009 ARM Limited. All rights reserved.ARM DDI 0331G