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The purpose of the Secure Debug Enable Register is to provide control of permissions for debug in Secure User mode, see Chapter 13 Debug.
Table 3.49 lists the purposes of the individual bits in the Secure Debug Enable Register.
The Secure Debug Enable Register is:
in CP15 c1
a 32 bit register in the Secure world only
accessible in Secure privileged modes only.
Figure 3.30 shows the arrangement of bits in the register.
Table 3.49 lists how the bit values correspond with the Secure Debug Enable Register functions.
Table 3.49. Secure Debug Enable Register bit functions
Bits | Field name | Function |
|---|---|---|
[31:2] | - | This field is UNP when read. Write as the existing value. |
| [1] | SUNIDEN | Enables Secure User non-invasive debug: 0 = Non-invasive debug is not permitted in Secure User mode, reset value 1 = Non-invasive debug is permitted in Secure User mode. |
| [0] | SUIDEN | Enables Secure User invasive debug: 0 = Invasive debug is not permitted in Secure User mode, reset value 1 = Invasive debug is permitted in Secure User mode. |
Table 3.50 lists the results of attempted access for each mode.
Table 3.50. Results of access to the Coprocessor Access Control Register
| Secure Privileged | Non-secure Privileged | User | |
|---|---|---|---|
| Read | Write | ||
| Data | Data | Undefined exception | Undefined exception |
To use the Secure Debug Enable Register read or write CP15 with:
Opcode_1 set to 0
CRn set to c1
CRm set to c1
Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c1, c1, 1 ; Read Secure Debug Enable Register
MCR p15, 0, <Rd>, c1, c1, 1 ; Write Secure Debug Enable Register