ARM1176JZ-S Technical Reference Manual: 3.2.18. c5, Instruction Fault Status Register

3.2.18. c5, Instruction Fault Status Register

The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last instruction fault.

Table 3.63 lists the purposes of the individual bits in IFSR.

The Instruction Fault Status Register is:

in CP15 c5
a 32-bit read/write register banked for Secure and Non-secure worlds
accessible in privileged modes only.

Figure 3.37 shows the bit arrangement of the Instruction Fault Status Register.

Figure 3.37. Instruction Fault Status Register format

Table 3.63 lists how the bit values correspond with the Instruction Fault Status Register functions.

Table 3.63. Instruction Fault Status Register bit functions

Bits	Field name	Function
[31:13]	-	UNP/SBZ.
[12]	SD	Indicates whether an AXI Decode or Slave error caused an abort. This bit is only valid for external aborts. For all other aborts this bit Should Be Zero. See Fault status and address: 0 = AXI Decode error caused the abort, reset value 1 = AXI Slave error caused the abort.
[11]	-	UNP/SBZ.
[10]	-	Part of the Status field, see bits [3:0] in this table. Always 0.
[9:4]	-	UNP/SBZ.
[3:0] with bit[10] = 0	Status	Indicates type of fault generated. See Fault status and address for full details of Domain and FAR validity, and priorities: b0000 = no function, reset value b0001= Alignment fault b0010 = Instruction debug event fault b0011 = Access Bit fault on Section b0100 = no function b0101 = Translation Section fault b0110 = Access Bit fault on Page b0111 = Translation Page fault b1000 = Precise external abort b1001 = Domain Section fault b1010 = no function b1011 = Domain Page fault b1100 = External abort on translation, first level b1101 = Permission Section fault b1110 = External abort on translation, second level b1111 = Permission Page fault.

Table 3.64 lists the results of attempted access for each mode.

Table 3.64. Results of access to the Instruction Fault Status Register

Secure Privileged		Non-secure Privileged		User
Read	Write	Read	Write	User
Secure data	Secure data	Non-secure data	Non-secure data	Undefined exception

Note

When the SCR EA bit is set, see c1, Secure Configuration Register, the processor writes to the Secure Instruction Fault Status Register on a Secure Monitor entry caused by an external abort.

To use the IFSR read or write CP15 with:

Opcode_1 set to 0
CRn set to c5
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c5, c0, 1    ; Read Instruction Fault Status Register

MCR p15, 0, <Rd>, c5, c0, 1    ; Write Instruction Fault Status Register

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