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The purpose of the Translation Table Base Register 1 is to hold the physical address of the first-level table. The expected use of the Translation Table Base Register 1 is for OS and I/O addresses.
Table 3.55 lists the purposes of the individual bits in the Translation Table Base Register 1.
The Translation Table Base Register 1 is:
in CP15 c2
a 32 bit read/write register banked for Secure and Non-secure worlds
accessible in privileged modes only.
Figure 3.33 shows the bit arrangement for the Translation Table Base Register 1.
Table 3.55 lists how the bit values correspond with the Translation Table Base Register 1 functions.
Table 3.55. Translation Table Base Register 1 bit functions
| Bits | Field name | Function |
|---|---|---|
| [31:14] | Translation table base 1 | Holds the translation table base address, the physical address of the first level translation table. The reset value is 0. |
| [13:5] | - | UNP/SBZ. |
| [4:3] | RGN | Indicates the Outer cacheable attributes for page table walking: b00 = Outer Noncacheable, reset value b01 = Write-back, Write Allocate b10 = Write-through, No Allocate on Write b11 = Write-back, No Allocate on Write. |
| [2] | P | If the processor supports ECC, it indicates to the memory controller it is enabled or disabled. For ARM1176JZ-S processors this is 0: 0 = Error-Correcting Code (ECC) is disabled, reset value 1 = ECC is enabled. |
| [1] | S | Indicates the page table walk is to Non-Shared or to Shared memory: 0 = Non-Shared, reset value 1 = Shared. |
| [0] | C | Indicates the page table walk is Inner Cacheable or Inner Non Cacheable: 0 = Inner Noncacheable, reset value 1 = Inner Cacheable. |
Table 3.56 lists the results of attempted access for each mode.
Table 3.56. Results of access to the Translation Table Base Register 1
| Secure Privileged | Non-secure Privileged | User | ||
|---|---|---|---|---|
| Read | Write | Read | Write | |
| Secure data | Secure data | Non-secure data | Non-secure data | Undefined exception |
A write to the Translation Table Base Register 1 updates the address of the first level translation table from the value in bits [31:14] of the written value. Bits [13:5] Should Be Zero. The Translation Table Base Register 1 must reside on a 16KB page boundary.
To use the Translation Table Base Register 1 read or write CP15 with:
Opcode_1 set to 0
CRn set to c2
CRm set to c0
Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c2, c0, 1 ; Read Translation Table Base Register 1
MCR p15, 0, <Rd>, c2, c0, 1 ; Write Translation Table Base Register 1
The ARM1176JZ-S processor cannot page table walk from level one cache. Therefore, if C is set to 1, to ensure coherency, you must either store page tables in Inner write-through memory or, if in Inner write-back, you must clean the appropriate cache entries after modification so that the mechanism for the hardware page table walks sees them.
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0333H |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control processor registers > c2, Translation Table Base Register 1 |