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The purpose of the DMA enable registers is to start, stop or clear DMA transfers for each channel implemented.
The DMA enable registers are:
in CP15 c11
three 32-bit write only registers for each DMA channel common to Secure and Non-secure worlds
accessible in user and privileged modes.
The commands that operate through the registers are:
The DMA channel ceases to do memory accesses as soon as possible after the level one DMA issues the instruction. This acceleration approach cannot be used for DMA transactions to or from memory regions marked as Device. The DMA can issue a Stop command when the channel status is Running. The DMA channel can take several cycles to stop after the DMA issues a Stop instruction. The channel status remains at Running until the DMA channel stops. The channel status is set to Complete or Error at the point that all outstanding memory accesses complete. The Start Address Registers contain the addresses the DMA requires to restart the operation when the channel stops.
If the Stop command occurs when the channel status is Queued, the channel status changes to Idle. The Stop command has no effect if the channel status is not Running or Queued.
c11, DMA Channel Status Register describes the DMA channel status.
The Start command causes the channel to start DMA transfers. If the other DMA channel is not in operation the channel status is set to Running on the execution of a Start command. If the other DMA channel is in operation the channel status is set to Queued.
A channel is in operation if either:
its channel status is Queued
its channel status is Running
its channel status is Complete or Error, with either the Internal or External Address Error Status indicating an Error.
c11, DMA Channel Status Register describes DMA channel status.
The Clear command causes the channel status to change from Complete or Error to Idle. It also clears:
all the Error bits for that DMA channel
the interrupt that is set by the DMA channel as a result of an error or completion, see c11, DMA Control Register for more details.
The Clear command does not change the contents of the Internal and External Start Address Registers. A Clear command has no effect when the channel status is Running or Queued.
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control Register. The processor can access these registers in User mode if the U bit, see c11, DMA User Accessibility Register, for the currently selected channel is set to 1. Table 3.111 lists the results of attempted access for each mode.
Table 3.111. Results of access to the DMA enable registers
| U bit | DMA bit | Secure Privileged | Non-secure Privileged | Secure User | Non-secure User | ||||
|---|---|---|---|---|---|---|---|---|---|
| Read | Write | Read | Write | Read | Write | Read | Write | ||
| 0 | 0 | Undefined exception | Data | Undefined exception | Undefined exception | Undefined exception | Undefined exception | Undefined exception | Undefined exception |
| 1 | Undefined exception | Data | Undefined exception | Data | Undefined exception | Undefined exception | Undefined exception | Undefined exception | |
| 1 | 0 | Undefined exception | Data | Undefined exception | Undefined exception | Undefined exception | Data | Undefined exception | Undefined exception |
| 1 | Undefined exception | Data | Undefined exception | Data | Undefined exception | Data | Undefined exception | Data | |
To access a DMA Enable Register set the DMA Channel Number Register to the appropriate DMA channel and write CP15 with:
Opcode_1 set to 3
CRn set to c11
CRm set to c3
Opcode_2 set to:
0, Stop
1, Start
2, Clear.
For example:
MCR p15, 0, <Rd>, c11, c3, 0 ; Stop DMA Enable Register
MCR p15, 0, <Rd>, c11, c3, 1 ; Start DMA Enable Register
MCR p15, 0, <Rd>, c11, c3, 2 ; Clear DMA Enable Register
The level one DMA behaves as a separate engine from the processor core, and when started, works autonomously. When the level one DMA has channels with the status of Running or Queued, these channels continue to run, or start running, even if a debug mechanism stops the processor. This can cause the contents of the TCM to change while the processor stops in debug. To avoid this situation you must ensure the level one DMA issues a Stop command to stop Running or Queued channels when entering debug.
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