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The DMA Context ID Register for each channel contains the processor 32-bit Context ID of the process that uses that channel.
The DMA Context ID Register is:
in CP15 c11
a 32-bit read/write register for each DMA channel common to Secure and Non-secure worlds
accessible in privileged modes only.
Figure 3.64 shows the arrangement of bits in the DMA Context ID Register.
Table 3.119 lists how the bit values correspond with the DMA Context ID Register functions.
Table 3.119. DMA Context ID Register bit functions
| Bits | Field name | Function |
|---|---|---|
| [31:8] | PROCID | Extends the ASID to form the process ID and identify the current process Holds the process ID value |
| [8:0] | ASID | Holds the ASID of the current process and identifies the current ASID Holds the ASID value |
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control Register. Table 3.120 lists the results of attempted access for each mode.
Table 3.120. Results of access to the DMA Context ID Register
| DMA bit | Secure Privileged | Non-secure Privileged | User | ||
|---|---|---|---|---|---|
| Read | Write | Read | Write | ||
| 0 | Data | Data | Undefined exception | Undefined exception | Undefined exception |
| 1 | Data | Data | Data | Data | Undefined exception |
To access the DMA Context ID register in a privileged mode set the DMA Channel Number Register to the appropriate DMA channel and read or write CP15 with:
Opcode_1 set to 0
CRn set to c11
CRm set to c15
Opcode_2 set to 0.
MRC p15, 0, <Rd>, c11, c15, 0 ; Read DMA Context ID Register
MCR p15, 0, <Rd>, c11, c15, 0 ; Write DMA Context ID Register
As part of the initialization of the DMA channel, the process that uses that channel writes the processor Context ID to the DMA Context ID Register. Where the channel is designated as a User-accessible channel, the privileged process, that initializes the channel for use in User mode, must write the Context ID at the same time that the software writes to the U bit for the channel.
The process that translates VAs to physical addresses uses the ASID stored in the bottom eight bits of the Context ID register to enable different VA maps to co-exist. Attempts to write this register while the DMA channel is Running or Queued has no effect.
Only privileged processes can read this register. This provides anonymity of the DMA channel usage from User processes. On a context switch, where the state of the DMA is stacked and restored, the saved state must include this register.
If a user process attempts to access this privileged register the processor takes an Undefined instruction trap.
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0333H |
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