ARM1176JZ-S Technical Reference Manual: 1.10.1. Extended ARM instruction set summary

1.10.1. Extended ARM instruction set summary

Table 1.5 summarizes the extended ARM instruction set.

Table 1.5. ARM instruction set summary

Operation		Assembler
Arithmetic	Add	`ADD{cond}{S} <Rd>, <Rn>, <operand2>`
	Add with carry	`ADC{cond}{S} <Rd>, <Rn>, <operand2>`
	Subtract	`SUB{cond}{S} <Rd>, <Rn>, <operand2>`
	Subtract with carry	`SBC{cond}{S} <Rd>, <Rn>, <operand2>`
	Reverse subtract	`RSB{cond}{S} <Rd>, <Rn>, <operand2>`
	Reverse subtract with carry	`RSC{cond}{S} <Rd>, <Rn>, <operand2>`
	Multiply	`MUL{cond}{S} <Rd>, <Rm>, <Rs>`
	Multiply-accumulate	`MLA{cond}{S} <Rd>, <Rm>, <Rs>, <Rn>`
	Multiply unsigned long	`UMULL{cond}{S} <RdLo>, <RdHi>, <Rm>, <Rs>`
	Multiply unsigned accumulate long	`UMLAL{cond}{S} <RdLo>, <RdHi>, <Rm>, <Rs>`
	Multiply signed long	`SMULL{cond}{S} <RdLo>, <RdHi>, <Rm>, <Rs>`
	Multiply signed accumulate long	`SMLAL{cond}{S} <RdLo>, <RdHi>, <Rm>, <Rs>`
	Saturating add	`QADD{cond} <Rd>, <Rm>, <Rn>`
	Saturating add with double	`QDADD{cond} <Rd>, <Rm>, <Rn>`
	Saturating subtract	`QSUB{cond} <Rd>, <Rm>, <Rn>`
	Saturating subtract with double	`QDSUB{cond} <Rd>, <Rm>, <Rn>`
	Multiply 16x16	`SMULxy{cond} <Rd>, <Rm>, <Rs>`
	Multiply-accumulate 16x16+32	`SMLAxy{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	Multiply 32x16	`SMULWy{cond} <Rd>, <Rm>, <Rs>`
	Multiply-accumulate 32x16+32	`SMLAWy{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	Multiply signed accumulate long 16x16+64	`SMLALxy{cond} <RdLo>, <RdHi>, <Rm>, <Rs>`
	Count leading zeros	`CLZ{cond} <Rd>, <Rm>`
Compare	Compare	`CMP{cond} <Rn>, <operand2>`
	Compare negative	`CMN{cond} <Rn>, <operand2>`
Logical	Move	`MOV{cond}{S} <Rd>, <operand2>`
	Move NOT	`MVN{cond}{S} <Rd>, <operand2>`
	Test	`TST{cond} <Rn>, <operand2>`
	Test equivalence	`TEQ{cond} <Rn>, <operand2>`
	AND	`AND{cond}{S} <Rd>, <Rn>, <operand2>`
	XOR	`EOR{cond}{S} <Rd>, <Rn>, <operand2>`
	OR	`ORR{cond}{S} <Rd>, <Rn>, <operand2>`
	Bit clear	`BIC{cond}{S} <Rd>, <Rn>, <operand2>`
	Copy	`CPY{<cond>} <Rd>, <Rm>`
Branch	Branch	`B{cond} <label>`
	Branch with link	`BL{cond} <label>`
	Branch and exchange	`BX{cond} <Rm>`
	Branch, link and exchange	`BLX <label>`
	Branch, link and exchange	`BLX{cond} <Rm>`
	Branch and exchange to Jazelle state	`BXJ{cond} <Rm>`
Status register handling	Move SPSR to register	`MRS{cond} <Rd>, SPSR`
	Move CPSR to register	`MRS{cond} <Rd>, CPSR`
	Move register to SPSR	`MSR{cond} SPSR_{field}, <Rm>`
	Move register to CPSR	`MSR{cond} CPSR_{field}, <Rm>`
	Move immediate to SPSR flags	`MSR{cond} SPSR_{field}, #<immed_8r>`
	Move immediate to CPSR flags	`MSR{cond} CPSR_{field}, #<immed_8r>`
Load	Word	`LDR{cond} <Rd>, <a_mode2>`
	Word with User mode privilege	`LDR{cond}T <Rd>, <a_mode2P>`
	PC as destination, branch and exchange	`LDR{cond} R15, <a_mode2P>`
	Byte	`LDR{cond}B <Rd>, <a_mode2>`
	Byte with User mode privilege	`LDR{cond}BT <Rd>, <a_mode2P>`
	Byte signed	`LDR{cond}SB <Rd>, <a_mode3>`
	Halfword	`LDR{cond}H <Rd>, <a_mode3>`
	Halfword signed	`LDR{cond}SH <Rd>, <a_mode3>`
	Doubleword	`LDR{cond}D <Rd>, <a_mode3>`
	Return from exception	`RFE<a_mode4> <Rn>{!}`
Load multiple	Stack operations	`LDM{cond}<a_mode4L> <Rn>{!}, <reglist>`
	Increment before	`LDM{cond}IB <Rn>{!}, <reglist>{^}`
	Increment after	`LDM{cond}IA <Rn>{!}, <reglist>{^}`
	Decrement before	`LDM{cond}DB <Rn>{!}, <reglist>{^}`
	Decrement after	`LDM{cond}DA <Rn>{!}, <reglist>{^}`
	Stack operations and restore CPSR	`LDM{cond}<a_mode4> <Rn>{!}, <reglist+pc>^`
	User registers	`LDM{cond}<a_mode4> <Rn>{!}, <reglist>^`
Soft preload	Memory system hint In Non-secure this instruction behaves like a `NOP`	`PLD <a_mode2>`
Store	Word	`STR{cond} <Rd>, <a_mode2>`
	Word with User mode privilege	`STR{cond}T <Rd>, <a_mode2P>`
	Byte	`STR{cond}B <Rd>, <a_mode2>`
	Byte with User mode privilege	`STR{cond}BT <Rd>, <a_mode2P>`
	Halfword	`STR{cond}H <Rd>, <a_mode3>`
	Doubleword	`STR{cond}D <Rd>, <a_mode3>`
	Store return state	`SRS<a_mode4> <mode>{!}`
Store multiple	Stack operations	`STM{cond}<a_mode4S> <Rn>{!}, <reglist>`
	User registers	`STM{cond}<a_mode4S> <Rn>, <reglist>^`
	Increment before	`STM{cond}IB, <Rn>{!}, <reglist>{^}`
	Increment after	`STM{cond}IA, <Rn>{!}, <reglist>{^}`
	Decrement before	`STM{cond}DB, <Rn>{!}, <reglist>{^}`
	Decrement after	`STM{cond}DA, <Rn>{!}, <reglist>{^}`
Swap	Word	`SWP{cond} <Rd>, <Rm>, [<Rn>]`
	Byte	`SWP{cond}B <Rd>, <Rm>, [<Rn>]`
Change state	Change processor state	`CPS<effect> <iflags>{, <mode>}`
	Change processor mode	`CPS <mode>`
	Change endianness	`SETEND <endian_specifier>`
NOP-compatible hints	No Operation	`NOP{<cond>}` `YIELD{<cond>}`
Byte-reverse	Byte-reverse word	`REV{cond} <Rd>, <Rm>`
	Byte-reverse halfword	`REV16{cond} <Rd>, <Rm>`
	Byte-reverse signed halfword	`REVSH{cond} <Rd>, <Rm>`
Synchronization primitives	Load exclusive	`LDREX{cond} <Rd>, [<Rn>`]
Synchronization primitives	Store exclusive	`STREX{cond} <Rd>, <Rm>, [<Rn>]`
	Load Byte Exclusive	LDREXB{cond} <Rxf>, [<Rbase>]
	Load Halfword Exclusive	LDREXH{cond} <Rd>, [<Rn>]
	Load Doubleword Exclusive	LDREXD{cond} <Rd>, [<Rn>]
	Store Byte Exclusive	STREXB{cond} <Rd>, <Rm>, [<Rn>]
	Store Halfword Exclusive	STREXH{cond} <Rd>, <Rm>, [<Rn>]
	Store Doubleword Exclusive	STREXD{cond} <Rd>, <Rm>, [<Rn>]
	Clear Exclusive	CLREX
Coprocessor	Data operations	`CDP{cond} <cp_num>, <op1>, <CRd>, <CRn>, <CRm>{, <op2>}`
	Move to ARM reg from coproc	`MRC{cond} <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}`
	Move to coproc from ARM reg	`MCR{cond} <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}`
	Move double to ARM reg from coproc	`MRRC{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm>`
	Move double to coproc from ARM reg	`MCRR{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm>`
	Load	`LDC{cond} <cp_num>, <CRd>, <a_mode5>`
	Store	`STC{cond} <cp_num>, <CRd>, <a_mode5>`
Alternative coprocessor	Data operations	`CDP2 <cp_num>, <op1>, <CRd>, <CRn>, <CRm>{, <op2>}`
Alternative coprocessor	Move to ARM reg from coproc	`MRC2 <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}`
	Move to coproc from ARM reg	`MCR2 <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}`
	Move double to ARM reg from coproc	`MRRC2 <cp_num>, <op1>, <Rd>, <Rn>, <CRm>`
	Move double to coproc from ARM reg	`MCRR2 <cp_num>, <op1>, <Rd>, <Rn>, <CRm>`
	Load	`LDC2 <cp_num>, <CRd>, <a_mode5>`
	Store	`STC2 <cp_num>, <CRd>, <a_mode5>`
Software interrupt		`SVC{cond} <immed_24>`
Secure Monitor Call		`SMC{cond} <immed_16>`
Software breakpoint		`BKPT <immed_16>`
Parallel add /subtract	Signed add high 16 + 16, low 16 + 16, set GE flags	`SADD16{cond} <Rd>, <Rn>, <Rm>`
	Saturated add high 16 + 16, low 16 + 16	`QADD16{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16 + 16, low 16 + 16, halved	`SHADD16{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 + 16, low 16 + 16, set GE flags	`UADD16{cond} <Rd>, <Rn>, <Rm>`
	Saturated unsigned high 16 + 16, low 16 + 16	`UQADD16{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 + 16, low 16 + 16, halved	`UHADD16{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16 + low 16, low 16 - high 16, set GE flags	`SADDSUBX{cond} <Rd>, <Rn>, <Rm>`
	Saturated high 16 + low 16, low 16 - high 16	`QADDSUBX{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16 + low 16, low 16 - high 16, halved	`SHADDSUBX{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 + low 16, low 16 - high 16, set GE flags	`UADDSUBX{cond} <Rd>, <Rn>, <Rm>`
	Saturated unsigned high 16 + low 16, low 16 - high 16	`UQADDSUBX{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 + low 16, low 16 - high 16, halved	`UHADDSUBX{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16 - low 16, low 16 + high 16, set GE flags	`SSUBADDX{cond} <Rd>, <Rn>, <Rm>`
	Saturated high 16 - low 16, low 16 + high 16	`QSUBADDX{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16 - low 16, low 16 + high 16, halved	`SHSUBADDX{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 - low 16, low 16 + high 16, set GE flags	`USUBADDX{cond} <Rd>, <Rn>, <Rm>`
	Saturated unsigned high 16 - low 16, low 16 + high 16	`UQSUBADDX{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 - low 16, low 16 + high 16, halved	`UHSUBADDX{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16-16, low 16-16, set GE flags	`SSUB16{cond} <Rd>, <Rn>, <Rm>`
	Saturated high 16 - 16, low 16 - 16	`QSUB16{cond} <Rd>, <Rn>, <Rm>`
	Signed high 16 - 16, low 16 - 16, halved	`SHSUB16{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 - 16, low 16 - 16, set GE flags	`USUB16{cond} <Rd>, <Rn>, <Rm>`
	Saturated unsigned high 16 - 16, low 16 - 16	`UQSUB16{cond} <Rd>, <Rn>, <Rm>`
	Unsigned high 16 - 16, low 16 - 16, halved	`UHSUB16{cond} <Rd>, <Rn>, <Rm>`
	Four signed 8 + 8, set GE flags	`SADD8{cond} <Rd>, <Rn>, <Rm>`
	Four saturated 8 + 8	`QADD8{cond} <Rd>, <Rn>, <Rm>`
	Four signed 8 + 8, halved	`SHADD8{cond} <Rd>, <Rn>, <Rm>`
	Four unsigned 8 + 8, set GE flags	`UADD8{cond} <Rd>, <Rn>, <Rm>`
	Four saturated unsigned 8 + 8	`UQADD8{cond} <Rd>, <Rn>, <Rm>`
	Four unsigned 8 + 8, halved	`UHADD8{cond} <Rd>, <Rn>, <Rm>`
	Four signed 8 - 8, set GE flags	`SSUB8{cond} <Rd>, <Rn>, <Rm>`
	Four saturated 8 - 8	`QSUB8{cond} <Rd>, <Rn>, <Rm>`
	Four signed 8 - 8, halved	`SHSUB8{cond} <Rd>, <Rn>, <Rm>`
	Four unsigned 8 - 8	`USUB8{cond} <Rd>, <Rn>, <Rm>`
	Four saturated unsigned 8 - 8	`UQSUB8{cond} <Rd>, <Rn>, <Rm>`
	Four unsigned 8 - 8, halved	`UHSUB8{cond} <Rd>, <Rn>, <Rm>`
	Sum of absolute differences	`USAD8{cond} <Rd>, <Rm>, <Rs>`
	Sum of absolute differences and accumulate	`USADA8{cond} <Rd>, <Rm>, <Rs>, <Rn>`
Sign/zero extend and add	Two low 8/16, sign extend to 16 + 16	`SXTAB16{cond} <Rd>, <Rn>, <Rm>{, <rotation>}`
	Low 8/32, sign extend to 32, + 32	`SXTAB{cond} <Rd>, <Rn>, <Rm>{, <rotation>}`
	Low 16/32, sign extend to 32, + 32	`SXTAH{cond} <Rd>, <Rn>, <Rm>{, <rotation>}`
	Two low 8/16, zero extend to 16, + 16	`UXTAB16{cond} <Rd>, <Rn>, <Rm>{, <rotation>}`
	Low 8/32, zero extend to 32, + 32	`UXTAB{cond} <Rd>, <Rn>, <Rm>{, <rotation>}`
	Low 16/32, zero extend to 32, + 32	`UXTAH{cond} <Rd>, <Rn>, <Rm>{, <rotation>}`
	Two low 8, sign extend to 16, packed 32	`SXTB16{cond} <Rd>, <Rm>{, <rotation>}`
	Low 8, sign extend to 32	`SXTB{cond} <Rd>, <Rm>{, <rotation>}`
	Low 16, sign extend to 32	`SXTH{cond} <Rd>, <Rm>{, <rotation>}`
	Two low 8, zero extend to 16, packed 32	`UXTB16{cond} <Rd>, <Rm>,{, <rotation>}`
	Low 8, zero extend to 32	`UXTB{cond} <Rd>, <Rm>{, <rotation>}`
	Low 16, zero extend to 32	`UXTH{cond} <Rd>, <Rm>{, <rotation>}`
Signed multiply and multiply, accumulate	Signed (high 16 x 16) + (low 16 x 16) + 32, and set Q flag.	`SMLAD{cond} <Rd>, <Rm>, <Rs>, <Rn>`
Signed multiply and multiply, accumulate	As `SMLAD`, but high x low, low x high, and set Q flag	`SMLADX{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	Signed (high 16 x 16) - (low 16 x 16) + 32	`SMLSD{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	As `SMLSD`, but high x low, low x high	`SMLSDX{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	Signed (high 16 x 16) + (low 16 x 16) + 64	`SMLALD{cond} <RdLo>, <RdHi>, <Rm>, <Rs>`
	As `SMLALD`, but high x low, low x high	`SMLALDX{cond} <RdLo>, <RdHi>, <Rm>, <Rs>`
	Signed (high 16 x 16) - (low 16 x 16) + 64	`SMLSLD{cond} <RdLo>, <RdHi>, <Rm>, <Rs>`
	As `SMLSLD`, but high x low, low x high	`SMLSLDX{cond} <RdLo>, <RdHi>, <Rm>, <Rs>`
	32 + truncated high 16 (32 x 32)	`SMMLA{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	32 + rounded high 16 (32 x 32)	`SMMLAR{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	32 - truncated high 16 (32 x 32)	`SMMLS{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	32 -rounded high 16 (32 x 32)	`SMMLSR{cond} <Rd>, <Rm>, <Rs>, <Rn>`
	Signed (high 16 x 16) + (low 16 x 16), and set Q flag	`SMUAD{cond} <Rd>, <Rm>, <Rs>`
	As `SMUAD`, but high x low, low x high, and set Q flag	`SMUADX{cond} <Rd>, <Rm>, <Rs>`
	Signed (high 16 x 16) - (low 16 x 16)	`SMUSD{cond} <Rd>, <Rm>, <Rs>`
	As `SMUSD`, but high x low, low x high	`SMUSDX{cond} <Rd>, <Rm>, <Rs>`
	Truncated high 16 (32 x 32)	`SMMUL{cond} <Rd>, <Rm>, <Rs>`
	Rounded high 16 (32 x 32)	`SMMULR{cond} <Rd>, <Rm>, <Rs>`
	Unsigned 32 x 32, + two 32, to 64	`UMAAL{cond} <RdLo>, <RdHi>, <Rm>, <Rs>`
Saturate, select, and pack	Signed saturation at bit position n	`SSAT{cond} <Rd>, #<immed_5>, <Rm>{, <shift>}`
	Unsigned saturation at bit position n	`USAT{cond} <Rd>, #<immed_5>, <Rm>{, <shift>}`
	Two 16 signed saturation at bit position n	`SSAT16{cond} <Rd>, #<immed_4>, <Rm>`
	Two 16 unsigned saturation at bit position n	`USAT16{cond} <Rd>, #<immed_4>, <Rm>`
	Select bytes from `Rn`/`Rm` based on GE flags	`SEL{cond} <Rd>, <Rn>, <Rm>`
	Pack low 16/32, high 16/32	`PKHBT{cond} <Rd>, <Rn>, <Rm>{, LSL #<immed_5>}`
	Pack high 16/32, low 16/32	`PKHTB{cond} <Rd>, <Rn>, <Rm>{, ASR #<immed_5>}`

Table 1.6 summarizes addressing mode 2.

Table 1.6. Addressing mode 2

Addressing mode		Assembler
Offset		-
	Immediate offset	`[<Rn>, #+/<immed_12>]`
	Zero offset	`[<Rn>]`
	Register offset	`[<Rn>, +/-<Rm>]`
	Scaled register offset	`[<Rn>, +/-<Rm>, LSL #<immed_5>]`
		`[<Rn>, +/-<Rm>, LSR #<immed_5>]`
		`[<Rn>, +/-<Rm>, ASR #<immed_5>]`
		`[<Rn>, +/-<Rm>, ROR #<immed_5>]`
		`[<Rn>, +/-<Rm>, RRX]`
Pre-indexed offset		-
	Immediate offset	`[<Rn>], #+/<immed_12>`
	Zero offset	`[<Rn>]`
	Register offset	`[<Rn>, +/-<Rm>]`!
	Scaled register offset	`[<Rn>, +/-<Rm>, LSL #<immed_5>]`!
		`[<Rn>, +/-<Rm>, LSR #<immed_5>]`!
		`[<Rn>, +/-<Rm>, ASR #<immed_5>]`!
		`[<Rn>, +/-<Rm>, ROR #<immed_5>]`!
		`[<Rn>, +/-<Rm>, RRX]`!
Post-indexed offset		-
	Immediate	`[<Rn>], #+/-<immed_12>`
	Zero offset	`[<Rn>]`
	Register offset	`[<Rn>], +/-<Rm>`
	Scaled register offset	`[<Rn>], +/-<Rm>, LSL #<immed_5>`
		`[<Rn>], +/-<Rm>, LSR #<immed_5>`
		`[<Rn>], +/-<Rm>, ASR #<immed_5>`
		`[<Rn>], +/-<Rm>, ROR #<immed_5>`
		`[<Rn>], +/-<Rm>, RRX`

Table 1.7 summarizes addressing mode 2P, post-indexed only.

Table 1.7. Addressing mode 2P, post-indexed only

Addressing mode		Assembler
Post-indexed offset		-
	Immediate offset	`[<Rn>], #+/-<immed_12>`
	Zero offset	`[<Rn>]`
	Register offset	`[<Rn>], +/-<Rm>`
	Scaled register offset	`[<Rn>], +/-<Rm>, LSL #<immed_5>`
		`[<Rn>], +/-<Rm>, LSR #<immed_5>`
		`[<Rn>], +/-<Rm>, ASR #<immed_5>`
		`[<Rn>], +/-<Rm>, ROR #<immed_5>`
		`[<Rn>], +/-<Rm>, RRX`

Table 1.8 summarizes addressing mode 3.

Table 1.8. Addressing mode 3

Addressing mode		Assembler
Immediate offset		`[<Rn>, #+/-<immed_8>]`
	Pre-indexed	`[<Rn>, #+/-<immed_8>]!`
	Post-indexed	`[<Rn>], #+/-<immed_8>`
Register offset		`[<Rn>, +/- <Rm>]`
	Pre-indexed	`[<Rn>, +/- <Rm>]!`
	Post-indexed	`[<Rn>], +/- <Rm>`

Table 1.9 summarizes addressing mode 4.

Table 1.9. Addressing mode 4

Addressing mode		Stack type
Block load		Stack pop (LDM, RFE)
IA	Increment after	FD	Full descending
IB	Increment before	ED	Empty descending
DA	Decrement after	FA	Full ascending
DB	Decrement before	EA	Empty ascending
Block store		Stack push (STM, SRS)
IA	IA Increment after	EA	Empty ascending
IB	IB Increment before	FA	Full ascending
DA	DA Decrement after	ED	Empty descending
DB	DB Decrement before	FD	Full descending

Table 1.10 summarizes addressing mode 5.

Table 1.10. Addressing mode 5

Addressing mode	Assembler
Immediate offset	`[<Rn>, #+/-<immed_8*4>]`
Immediate pre-indexed	`[<Rn>, #+/-<immed_8*4>]!`
Immediate pre-indexed	`[<Rn>], #+/-<immed_8*4>`
Unindexed	`[<Rn>], <option>`

Table 1.11 summarizes Operand2 assembler.

Table 1.11. Operand2

Operation	Assembler
Immediate value	`#<immed_8r>`
Logical shift left	`<Rm> LSL #<immed_5>`
Logical shift right	`<Rm> LSR #<immed_5>`
Arithmetic shift right	`<Rm> ASR #<immed_5>`
Rotate right	`<Rm> ROR #<immed_5>`
Register	`<Rm>`
Logical shift left	`<Rm> LSL <Rs>`
Logical shift right	`<Rm> LSR <Rs>`
Arithmetic shift right	`<Rm> ASR <Rs>`
Rotate right	`<Rm> ROR <Rs>`
Rotate right extended	`<Rm> RRX`

Table 1.12 summarizes the MSR instruction fields.

Table 1.12. Fields

Suffix	Sets this bit in the MSR field_mask	MSR instruction bit number
`c`	Control field mask bit, bit 0	16
`x`	Extension field mask bit, bit 1	17
`s`	Status field mask bit, bit 2	18
`f`	Flags field mask bit, bit 3	19

Table 1.13 summarizes condition codes.

Table 1.13. Condition codes

Suffix	Description
`EQ`	Equal
`NE`	Not equal
`HS/CS`	Unsigned higher or same, carry set
`LO/CC`	Unsigned lower, carry clear
`MI`	Negative, minus
`PL`	Positive or zero, plus
`VS`	Overflow
`VC`	No overflow
`HI`	Unsigned higher
`LS`	Unsigned lower or same
`GE`	Signed greater or equal
`LT`	Signed less than
`GT`	Signed greater than
`LE`	Signed less than or equal
`AL`	Always

Copyright © 2004-2009 ARM Limited. All rights reserved.	ARM DDI 0333H
Non-Confidential
PDF version