ARM1176JZ-S Technical Reference Manual: 4.5.2. ARMv6 support for mixed-endian data

4.5.2. ARMv6 support for mixed-endian data

In ARMv6 the instruction and data endianness are separated:

instructions are fixed little-endian
data accesses can be either little-endian or big-endian as controlled by bit 9, the E bit, of the Program Status Register.

The value of the E bit on any exception entry, including reset, is determined by the CPSR Register 15 EE bit.

Fixed little-endian Instructions

Instructions must be naturally aligned and are always treated as being stored in memory in little-endian format. That is, the PC points to the least-significant-byte of the instruction.

Instructions must be treated as data by exception handlers, decoding SVC calls and Undefined instructions, for example.

Instructions can also be written as data by debuggers, Just-In-Time (JIT) compilers, or in operating systems that update exception vectors.

Mixed-endian data access

The operating-system typically has a required endian representation of internal data structures, but applications and device drivers have to work with data shared with other processors, DSP or DMA interfaces, that might have fixed big-endian or little-endian data formatting.

A byte-invariant addressing mechanism is provided that enables the load/store architecture to be qualified by the CPSR E bit that provides byte reversing of big-endian data in to, and out of, the processor register bank transparently. This byte-invariant big-endian representation is referred to as BE-8 in this document.

Mixed-endian configuration supported describes the effect on byte, halfword, word, and multi-word accesses of setting the CPSR E bit when the U bit enables unaligned support.

Byte data access

The same physical byte in memory is accessed whether big-endian, BE-8, or little-endian:

unsigned byte load as Load unsigned byte, endian independent describes
signed byte load as Load signed byte, endian independent describes
byte store as Store byte, endian independent describes.

Halfword data access

The same two physical bytes in memory are accessed whether big-endian, BE-8, or little-endian. Big-endian halfword load data is byte-reversed as read into the processor register to ensure little-endian internal representation, and similarly is byte-reversed on store to memory:

unsigned halfword load as Load unsigned halfword, little-endian, LE, and Load unsigned halfword, big-endian, BE-8 describe
signed halfword load as Load signed halfword, little-endian, LE, and Load signed halfword, big-endian, BE-8 describe
halfword store as Store halfword, little-endian, LE, and Store halfword, big-endian, BE-8 describe.

Word data access

The same four physical bytes in memory are accessed whether big-endian, BE-8, or little-endian. Big-endian word load data is byte reversed as read into the processor register to ensure little-endian internal representation, and similarly is byte-reversed on store to memory:

word load as Load word, little-endian, LE, and Load word, big-endian, BE-8 describes
word store as Store word, little-endian, LE, and Store word, big-endian, BE-8 describes.

Mixed-endian configuration supported

This behavior is enabled when the U bit in CP15 Register c1 is set. This is only supported when the B bit in CP15 Register c1 is reset, as Table 4.5 lists.

Table 4.5. Mixed-endian configuration

U	B	E	Instruction endianness	Data endianness	Description
1	0	0	LE	LE	LE instructions, little-endian data load/store. Unaligned data access permitted.
1	0	1	LE	BE-8	LE instructions, big-endian data load/store. Unaligned data access permitted.
1	1	0	BE-32	BE-32	Legacy BE instructions/data.
1	1	1	-	-	Reserved.

Copyright © 2004-2009 ARM Limited. All rights reserved.	ARM DDI 0333H
Non-Confidential
PDF version