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The Debug Status and Control Register contains status and configuration information about the state of the debug system. Figure 13.3 shows the format of the Debug Status and Control Register.
Table 13.4 lists the bit field definitions for the Debug Status and Control Register.
Table 13.4. Debug Status and Control Register bit field definitions
| Bits | Core view | External view | Reset value | Description |
|---|---|---|---|---|
| [31] | UNP/SBZP | UNP/SBZP | - | Reserved. |
| [30] | R | R | 0 | The rDTRfull flag: 0 = rDTR empty 1 = rDTR full. This flag is automatically set on writes by the DBGTAP debugger to the rDTR and is cleared on reads by the core of the same register. No writes to the rDTR are enabled if the rDTRfull flag is set. |
| [29] | R | R | 0 | The wDTRfull flag: 0 = wDTR empty 1 = wDTR full. This flag is automatically cleared on reads by the DBGTAP debugger of the wDTR and is set on writes by the core to the same register. |
| [28:20] | UNP/SBZP | UNP/SBZP | - | Reserved. |
| [19] | R | R | 0 | Imprecise Data Aborts Ignored. This read-only bit is set by the core in Debug state following a Data Memory Barrier operation, and cleared on exit from Debug state. When set, the core does not act on imprecise data aborts. However, the sticky imprecise data abort bit is set if an imprecise data abort occurs when in Debug state. |
| [18] | R | R | 0 | Non-secure World Status bit 0 = The processor is in Secure state. NS bit = 0 or Secure Monitor mode.1 = The processor is in Non-secure state. NS bit = 1 and not Secure Monitor mode. |
| [17] | R | R | n/a | Not Secure Privilege Non-Invasive Debug Enable, SPNIDEN, input pin.0 = SPNIDEN input pin is HIGH.1 = SPNIDEN input pin is LOW. |
| [16] | R | R | n/a | Not Secure Privilege Invasive Debug Enable, SPIDEN, input pin.0 = SPIDEN input pin is HIGH.1 = SPIDEN input pin is LOW. |
| [15] | RW | R | 0 | The Monitor debug-mode enable bit: 0 = Monitor debug-mode disabled 1 = Monitor debug-mode enabled. For the core to take a debug exception, Monitor debug-mode has to be both selected and enabled, bit 14 clear and bit 15 set. |
| [14] | R | RW | 0 | Mode select bit: 0 = Monitor debug-mode selected 1 = Halting debug-mode selected and enabled. |
| [13] | R | RW | 0 | Execute ARM instruction enable bit: 0 = Disabled 1 = Enabled. If this bit is set, the core can be forced to execute ARM instructions in Debug state using the Debug Test Access Port. If this bit is set when the core is not in Debug state, the behavior of the processor is architecturally Unpredictable. For ARM1176JZ-S processors it has no effect. |
| [12] | RW | R | 0 | User mode access to comms channel control bit: 0 = User mode access to comms channel enabled 1 = User mode access to comms channel disabled. If this bit is set and a User mode process tries to access the DIDR, DSCR, or the DTR, the Undefined instruction exception is taken. Because accessing the rest of CP14 debug registers is never possible in User mode, see Executing CP14 debug instructions, setting this bit means that a User mode process cannot access any CP14 debug register. |
| [11] | R | RW | 0 | Interrupts bit: 0 = Interrupts enabled 1 = Interrupts disabled. If this bit is set, the IRQ and FIQ input signals are inhibited.[a] |
| [10] | R | RW | 0 | DbgAck bit. If this bit is set, the DBGACK output signal (see External signals) is forced HIGH, regardless of the processor state.a |
| [9] | R | RW | 0 | Powerdown disable: 0 = DBGNOPWRDWN is LOW 1 = DBGNOPWRDWN is HIGH. See External signals. |
| [8] | R | RC | 0 | Sticky Undefined flag: 0 = No Undefined exception trap occurred in Debug state since the last time this bit was cleared. 1 = An undefined exception occurred while in Debug state since the last time this bit was cleared. This bit is cleared on reads of a DBGTAP debugger to the DSCR. The Sticky Undefined bit does not prevent additional instructions from being issued. The Sticky Undefined bit is not set by Undefined exceptions occurring when not in Debug state. |
| [7] | R | RC | 0 | Sticky imprecise Data Aborts flag: 0 = No imprecise Data Aborts occurred since the last time this bit was cleared 1 = An imprecise Data Abort has occurred since the last time this bit was cleared. It is cleared on reads of a DBGTAP debugger to the DSCR. The sticky imprecise data abort bit is only set by imprecise data aborts occurring when in Debug state. NoteIn previous versions of the debug architecture, the sticky imprecise data abort was set when the processor took an imprecise data abort. In version 6.1, it is set when an imprecise data abort is detected. |
| [6] | R | RC | 0 | Sticky precise Data Abort flag: 0 = No precise Data Abort occurred since the last time this bit was cleared 1 = A precise Data Abort has occurred since the last time this bit was cleared. This flag is meant to detect Data Aborts generated by instructions issued to the processor using the Debug Test Access Port. Therefore, if the DSCR[13] execute ARM instruction enable bit is a 0, the value of the sticky precise Data Abort bit is architecturally Unpredictable. For ARM1176JZ-S processors the sticky precise Data Abort bit is set regardless of DSCR[13]. It is cleared on reads of a DBGTAP debugger to the DSCR. The sticky precise data abort bit is only set by precise data aborts occurring when in Debug state. |
| [5:2] | RW | R | b0000 | Method of debug entry bits: b0000 = a Halt DBGTAP instruction occurred b0001 = a breakpoint occurred b0010 = a watchpoint occurred b0011 = a BKPT instruction occurred b0100 = an EDBGRQ signal activation occurred b0101 = a vector catch occurred b0110 = reserved b0111 = reserved b1xxx = reserved. These bits are set to indicate any of:
A Prefetch Abort or Data Abort handler must first check the IFSR or DFSR register to determine a debug exception has occurred before checking the DSCR to find the cause. These bits are not set on any events in Debug state. |
| [1] | R | R | 1 | Core restarted bit: 0 = the processor is exiting Debug state 1 = the processor has exited Debug state. The DBGTAP debugger can poll this bit to determine when the processor has exited Debug state. See Debug state for a definition of Debug state. |
| [0] | R | R | 0 | Core halted bit: 0 = the processor is in normal state 1 = the processor is in Debug state. The DBGTAP debugger can poll this bit to determine when the processor has entered Debug state. See Debug state for a definition of Debug state. |
[a] Bits DSCR[11:10] can be controlled by a DBGTAP debugger to execute code in normal state as part of the debugging process. For example, if the DBGTAP debugger has to execute an OS service to bring a page from disk into memory, and then return to the application to see the effect this change of state produces, it is undesirable that interrupts are serviced during execution of this routine. | ||||
Bits [5:2] are set to indicate:
the reason for jumping to the Prefetch or Data Abort vector
the reason for entering Debug state.
A prefetch abort or data abort handler determines if it must jump to the debug monitor target by examining the IFSR or DFSR respectively. A DBGTAP debugger or debug monitor target can determine the specific debug event that caused the Debug state or debug exception entry by examining DSCR[5:2].
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