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The maximum timing parameter or constraint delay for each processor signal applied to the SoC is given as a percentage in Table 17.1 to Table 17.8. The input delay columns provide the maximum and minimum time as a percentage of the processor clock cycle given to the SoC for that signal.
The maximum delay timing parameter or constraint permitted for all processor output signals enables 60% of the processor clock cycle to the SoC.
Table 17.1 lists the global signal timing parameters.
Table 17.1. Global signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| ACLKEND | Clock uncertainty | 40 |
| ACLKENI | Clock uncertainty | 40 |
| ACLKENP | Clock uncertainty | 40 |
| ACLKENRW | Clock uncertainty | 40 |
| ARESETDn | Clock uncertainty | 20 |
| ARESETIn | Clock uncertainty | 20 |
| ARESETPn | Clock uncertainty | 20 |
| ARESETRWn | Clock uncertainty | 20 |
| nPORESETIN | Clock uncertainty | 20 |
| nRESETIN | Clock uncertainty | 20 |
| nVFPRESETIN | Clock uncertainty | 20 |
| RAMCLAMP | Clock uncertainty | 20 |
| SYNCMODEREQD | Clock uncertainty | 60 |
| SYNCMODEREQI | Clock uncertainty | 60 |
| SYNCMODEREQP | Clock uncertainty | 60 |
| SYNCMODEREQRW | Clock uncertainty | 60 |
| VFPCLAMP | Clock uncertainty | 20 |
Table 17.2 lists the AXI interface timing parameters.
Table 17.2. AXI signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| ARREADYD | Clock uncertainty | 50 |
| ARREADYI | Clock uncertainty | 50 |
| ARREADYP | Clock uncertainty | 50 |
| ARREADYRW | Clock uncertainty | 50 |
| BRESPD[1:0] | Clock uncertainty | 70 |
| BRESPP[1:0] | Clock uncertainty | 70 |
| BRESPRW[1:0] | Clock uncertainty | 70 |
| BVALIDD | Clock uncertainty | 50 |
| BVALIDP | Clock uncertainty | 50 |
| BVALIDRW | Clock uncertainty | 50 |
| RDATAD[63:0] | Clock uncertainty | 70 |
| RDATAI[63:0] | Clock uncertainty | 70 |
| RDATAP[31:0] | Clock uncertainty | 70 |
| RDATARW[63:0] | Clock uncertainty | 70 |
| RLASTD | Clock uncertainty | 70 |
| RLASTI | Clock uncertainty | 70 |
| RLASTP | Clock uncertainty | 70 |
| RLASTRW | Clock uncertainty | 70 |
| RRESPD[1:0] | Clock uncertainty | 70 |
| RRESPI[1:0] | Clock uncertainty | 70 |
| RRESPP[1:0] | Clock uncertainty | 70 |
| RRESPRW[1:0] | Clock uncertainty | 70 |
| RVALIDD | Clock uncertainty | 50 |
| RVALIDI | Clock uncertainty | 50 |
| RVALIDP | Clock uncertainty | 50 |
| RVALIDRW | Clock uncertainty | 50 |
| WREADYD | Clock uncertainty | 50 |
| WREADYP | Clock uncertainty | 50 |
| WREADYRW | Clock uncertainty | 50 |
Table 17.3 lists the coprocessor port timing parameters.
Table 17.3. Coprocessor signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| CPAACCEPT | Clock uncertainty | 70 |
| CPAACCEPTHOLD | Clock uncertainty | 70 |
| CPAACCEPTT [3:0] | Clock uncertainty | 70 |
| CPALENGTH [3:0] | Clock uncertainty | 70 |
| CPALENGTHHOLD | Clock uncertainty | 70 |
| CPALENGTHT [3:0] | Clock uncertainty | 70 |
| CPAPRESENT[11:0] | Clock uncertainty | 70 |
| CPASTDATA [63:0] | Clock uncertainty | 70 |
| CPASTDATAT [3:0] | Clock uncertainty | 70 |
| CPASTDATAV | Clock uncertainty | 70 |
Table 17.4 lists the ETM interface port timing parameters.
Table 17.4. ETM interface signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
ETMEXTOUT[1:0] | Clock uncertainty | 60 |
ETMPWRUP | Clock uncertainty | 60 |
nETMWFIREADY | Clock uncertainty | 60 |
ETMCPRDATA[31:0] | Clock uncertainty | 60 |
Table 17.5 lists the interrupt port timing parameters.
Table 17.5. Interrupt signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| INTSYNCEN | Clock uncertainty | 60 |
| IRQADDR[31:2] | Clock uncertainty | 60 |
| IRQADDRV | Clock uncertainty | 60 |
| IRQADDRVSYNCEN | Clock uncertainty | 60 |
| nFIQ | Clock uncertainty | 60 |
| nIRQ | Clock uncertainty | 60 |
Table 17.6 lists the debug timing parameters.
Table 17.6. Debug interface signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| TCK | Clock uncertainty | 20 |
| JTAGSYNCBYPASS | Clock uncertainty | 20 |
| DBGnTRST | Clock uncertainty | 60 |
| TDI | Clock uncertainty | 20 |
| TMS | Clock uncertainty | 20 |
| EDBGRQ | Clock uncertainty | 60 |
| DBGEN | Clock uncertainty | 60 |
| DBGVERSION[3:0] | Clock uncertainty | 50 |
| DBGMANID[10:0] | Clock uncertainty | 50 |
| SPIDEN | Clock uncertainty | 60 |
| SPNIDEN | Clock uncertainty | 60 |
Table 17.7 lists the test port timing parameters.
Table 17.7. Test signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| SE | Clock uncertainty | 20 |
| RSTBYPASS | Clock uncertainty | 20 |
| MTESTON | Clock uncertainty | 60 |
| MBISTDIN[63:0] | Clock uncertainty | 60 |
| MBISTADDR[12:0] | Clock uncertainty | 60 |
| MBISTCE[19:0] | Clock uncertainty | 60 |
| MBISTWE[7:0] | Clock uncertainty | 60 |
| MBISTDOUT[63:0] | Clock uncertainty | 40 |
Table 17.8 lists the static configuration signal port timing parameters.
Table 17.8. Static configuration signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| BIGENDINIT | Clock uncertainty | 60 |
| INITRAM | Clock uncertainty | 60 |
| UBITINIT | Clock uncertainty | 60 |
| VINITHI | Clock uncertainty | 60 |
Table 17.9 lists the internal TrustZone signal port timing parameters.
Table 17.9. TrustZone internal signals
| Name | Minimum input delay | Maximum input delay% |
|---|---|---|
| CP15SDISABLE | Clock uncertainty | 60 |
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0333H |
| Non-Confidential | |
| PDF version | |
| Home > AC Characteristics > Processor timing parameters |