3.2.1. Register allocation

Table 3.2 lists the allocation and reset values of the registers of the system control coprocessor where:

Table 3.2. Summary of CP15 registers and operations

CRnOp1CRmOp2Register or operationS typeNS typeReset valuePage
c00c00Main ID RORO0x41xFB76x [a]c0, Main ID Register
1Cache TypeRORO0x10152152 [b]c0, Cache Type Register
2TCM StatusRORO0x00020002 [c]c0, TCM Status Register
3TLB TypeRORO0x00000800c0, TLB Type Register
c10Processor Feature 0RORO0x00000111c0, Processor Feature Register 0
1Processor Feature 1RORO0x00000011c0, Processor Feature Register 1
2Debug Feature 0RORO0x00000033c0, Debug Feature Register 0
3Auxiliary Feature 0RORO0x00000000c0, Auxiliary Feature Register 0
4Memory Model Feature 0RORO0x01130003c0, Memory Model Feature Register 0
5Memory Model Feature 1RORO0x10030302c0, Memory Model Feature Register 1
6Memory Model Feature 2RORO0x01222100c0, Memory Model Feature Register 2
7Memory Model Feature 3RORO0x00000000c0, Memory Model Feature Register 3
c20Instruction Set Feature Attribute 0RORO0x00140011c0, Instruction Set Attributes Register 0
1Instruction Set Feature Attribute 1RORO0x12002111c0, Instruction Set Attributes Register 1
2Instruction Set Feature Attribute 2RORO0x11231121c0, Instruction Set Attributes Register 2
3Instruction Set Feature Attribute 3RORO0x01102131c0, Instruction Set Attributes Register 3
4Instruction Set Feature Attribute 4RORO0x00001141c0, Instruction Set Attributes Register 4
5Instruction Set Feature Attribute 5RORO0x00000000c0, Instruction Set Attributes Register 5
6-7Reserved----
c3-c7-Reserved----
c10c00ControlR/W, B[d], XR/W0x00050078[e]c1, Control Register
1Auxiliary ControlR/WRO0x00000007c1, Auxiliary Control Register
2Coprocessor Access ControlR/WR/W0x00000000c1, Coprocessor Access Control Register
c10Secure ConfigurationR/WNA0x00000000c1, Secure Configuration Register
1Secure Debug EnableR/WNA0x00000000c1, Secure Debug Enable Register
2Non-Secure Access ControlR/WRO0x00000000c1, Non-Secure Access Control Register
c20c00Translation Table Base 0R/W, B, XR/W0x00000000c2, Translation Table Base Register 0
1Translation Table Base 1R/W, BR/W0x00000000c2, Translation Table Base Register 1
2Translation Table Base ControlR/W, B, XR/W0x00000000c2, Translation Table Base Control Register
c30c00Domain Access ControlR/W, B, XR/W0x00000000c3, Domain Access Control Register
c4Not used 
c50c00Data Fault StatusR/W, BR/W0x00000000c5, Data Fault Status Register
1Instruction Fault StatusR/W, BR/W0x00000000c5, Instruction Fault Status Register
c60c00Fault AddressR/W, BR/W0x00000000c6, Fault Address Register
1Watchpoint Fault AddressR/WNA0x00000000c6, Watchpoint Fault Address Register
2Instruction Fault AddressR/W, BR/W0x00000000c6, Instruction Fault Address Register
c70c04Wait For InterruptWOWO-Wait For Interrupt operation
c40PAR/W, BR/W0x00000000PA Register
c50Invalidate Entire Instruction CacheWOWO, X-Invalidate, Clean, and Prefetch operations
1Invalidate Instruction Cache Line by MVAWOWO-Invalidate, Clean, and Prefetch operations
2Invalidate Instruction Cache Line by IndexWOWO-Invalidate, Clean, and Prefetch operations
4Flush Prefetch BufferWOWO-Flush operations
6Flush Entire Branch Target CacheWOWO-Flush operations
7Flush Branch Target Cache Entry by MVAWOWO-Flush operations
c60Invalidate Entire Data CacheWONA-Invalidate, Clean, and Prefetch operations
1Invalidate Data Cache Line by MVAWOWO-Invalidate, Clean, and Prefetch operations
2Invalidate Data Cache Line by IndexWOWO-Invalidate, Clean, and Prefetch operations
c70Invalidate Both CachesWONA-Invalidate, Clean, and Prefetch operations
c80-3VA to PA translation in the current worldWOWO-VA to PA translation in the current world
4-7VA to PA translation in the other worldWONA-VA to PA translation in the other world
c70c100Clean Entire Data CacheWO, XWO, X-Invalidate, Clean, and Prefetch operations
1Clean Data Cache Line by MVAWOWO-Invalidate, Clean, and Prefetch operations
2Clean Data Cache Line by IndexWOWO-Invalidate, Clean, and Prefetch operations
4Data Synchronization BarrierWOWO-Data Synchronization Barrier operation
5Data Memory BarrierWOWO-Data Memory Barrier operation
6Cache Dirty StatusRO, BRO0x00000000Cache Dirty Status Register
c131Prefetch Instruction Cache LineWOWO-Invalidate, Clean, and Prefetch operations
c140Clean and Invalidate Entire Data CacheWO, XWO, X-Invalidate, Clean, and Prefetch operations
1Clean and Invalidate Data Cache Line by MVAWOWO-Invalidate, Clean, and Prefetch operations
2Clean and Invalidate Data Cache Line by IndexWOWO-Invalidate, Clean, and Prefetch operations
c80c50Invalidate Instruction TLB unlocked entriesWO, BWO-c8, TLB Operations Register
1Invalidate Instruction TLB entry by MVAWO, BWO-c8, TLB Operations Register
2Invalidate Instruction TLB entry on ASID matchWO, BWO-c8, TLB Operations Register
c80c60Invalidate Data TLB unlocked entriesWO, BWO-c8, TLB Operations Register
1Invalidate Data TLB entry by MVAWO, BWO-c8, TLB Operations Register
2Invalidate Data TLB entry on ASID matchWO, BWO-c8, TLB Operations Register
c70Invalidate unified TLB unlocked entriesWO, BWO-c8, TLB Operations Register
1Invalidate unified TLB entry by MVAWO, BWO-c8, TLB Operations Register
2Invalidate unified TLB entry on ASID matchWO, BWO-c8, TLB Operations Register
c90c00Data Cache LockdownR/WR/W, X0xFFFFFFF0c9, Data and instruction cache lockdown registers
1Instruction Cache LockdownR/WR/W, X0xFFFFFFF0c9, Data and instruction cache lockdown registers
c10Data TCM RegionR/W, XR/W, X0x00000014[f]c9, Data TCM Region Register
1Instruction TCM RegionR/W, XR/W, X0x00000014[g]c9, Instruction TCM Region Register
2Data TCM Non-secure Control AccessR/W, XNA0x00000000c9, Data TCM Non-secure Control Access Register
3Instruction TCM Non-secure Control AccessR/W, XNA0x00000000c9, Instruction TCM Non-secure Control Access Register
c20TCM SelectionR/W, BR/W0x00000000c9, TCM Selection Register
c80Cache Behavior OverrideR/W[h]R/W0x00000000c9, Cache Behavior Override Register
c100c00TLB LockdownR/W, XR/W, X0x00000000c10, TLB Lockdown Register
c20Primary Region Memory Remap RegisterR/W, B, XR/W0x00098AA4c10, Memory region remap registers
1Normal Memory Region Remap RegisterR/W, B, XR/W0x44E048E0c10, Memory region remap registers
c110c00-3DMA identification and statusRORO, X0x0000000B[i]c11, DMA identification and status registers
c10DMA User AccessibilityR/WR/W, X0x00000000c11, DMA User Accessibility Register
c20DMA Channel NumberR/W, XR/W, X0x00000000c11, DMA Channel Number Register
c30-2DMA enableWO, XWO, X-c11, DMA enable registers
c40DMA ControlR/W, XR/W, X0x08000000c11, DMA Control Register
c50DMA Internal Start AddressR/W, XR/W, X-c11, DMA Internal Start Address Register
c60DMA External Start AddressR/W, XR/W, X-c11, DMA External Start Address Register
c70DMA Internal End AddressR/W, XR/W, X-c11, DMA Internal End Address Register
c80DMA Channel StatusRO, XRO, X0x00000000c11, DMA Channel Status Register
c150DMA Context IDR/WR/W, X-c11, DMA Context ID Register
c120c00Secure or Non-secure Vector Base AddressR/W, B, XR/W0x00000000c12, Secure or Non-secure Vector Base Address Register
1Monitor Vector Base AddressR/W, XNA0x00000000c12, Monitor Vector Base Address Register
c10Interrupt StatusRORO0x00000000[j]c12, Interrupt Status Register
c130c00FCSE PIDR/W, B, XR/W0x00000000c13, FCSE PID Register
1Context IDR/W, BR/W0x00000000c13, Context ID Register
2User Read/Write Thread and Process IDR/W, BR/W0x00000000c13, Thread and process ID registers
3User Read-only Thread and Process IDR/W, RO, B[k]R/W, RO0x00000000c13, Thread and process ID registers
4Privileged Only Thread and Process IDR/W, BR/W0x00000000c13, Thread and process ID registers
c14Not used 
c150c24Peripheral Port Memory RemapR/W, B, XR/W0x00000000c15, Peripheral Port Memory Remap Register
c90Secure User and Non-secure Access Validation ControlR/W, XNA0x00000000c15, Secure User and Non-secure Access Validation Control Register
c120Performance Monitor ControlR/W, XR/W, X0x00000000c15, Performance Monitor Control Register
1Cycle CounterR/W, XR/W, X0x00000000c15, Cycle Counter Register
2Count 0R/W, XR/W, X0x00000000c15, Count Register 0
3Count 1R/W, XR/W, X0x00000000c15, Count Register 1
4-7System Validation CounterR/W, XR/W, X0x00000000c15, System Validation Counter Register
c131-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c140System Validation Cache Size MaskR/W, XR/W, X0x00006655[l]c15, System Validation Cache Size Mask Register
c151c130-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c152c131-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c153c80-7Instruction Cache Master ValidR/W, XNA0x00000000c15, Instruction Cache Master Valid Register
c120-7Data Cache Master ValidR/W, XNA0x00000000c15, Data Cache Master Valid Register
c130-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c154c130-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c155c42TLB Lockdown IndexR/W, XNA0x00000000c15, TLB lockdown access registers
c52TLB Lockdown VAR/W, XNA-c15, TLB lockdown access registers
c62TLB Lockdown PAR/W, XNA-c15, TLB lockdown access registers
c72TLB Lockdown AttributesR/W, XNA-c15, TLB lockdown access registers
c130-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c156c130-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register
c157c130-7System Validation OperationsR/W, XR/W, X0x00000000c15, System Validation Operations Register

[a] See c0, Main ID Register for the values of bits [23:20] and bits [3:0].

[b] Reset value depends on the cache size implemented. The value here is for 16KB instruction and data caches.

[c] Reset value depends on the number of TCM banks implemented. The value here is for 2 data TCM and 2 instruction TCM banks.

[d] Some bits in this register are banked and some Secure modify only.

[e] Reset value depends on external signals.

[f] Reset value depends on the TCM sizes implemented. The value here is for 16KB TCM banks.

[g] Reset value depends on the TCM sizes implemented, and on the value of the INITRAM static configuration signal. The value here is for 16KB TCM banks, with INITRAM tied LOW.

[h] Some bits in this register are common and some Secure modify only.

[i] Reset value depends on the number of DMA channels implemented and the presence of TCMs.

[j] Reset value depends on external signals.

[k] This register is read/write in Privileged modes and read-only on User mode.

[l] Reset value depends on the cache and TCM sizes implemented. The value here is for 2 banks of 16KB instruction and data TCMs and 16KB instruction and data caches.


Table 3.3 lists the operations available with MCRR operations:

MCRR{cond} P15,<Opcode_1>,<End Address>,<Start Address>,<CRm>

Table 3.3. Summary of CP15 MCRR operations

Op1CRmRegister or operationS typeNS typeReset valuePage
0c5Invalidate instruction cache rangeWOWO-c7, Cache operations
c6Invalidate data cache rangeWOWO-c7, Cache operations
c12Clean data cache rangeWOWO-c7, Cache operations
c14Clean and invalidate data cache rangeWOWO-c7, Cache operations

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