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When the CP15 Control Register c1 Bit 23 is set to 1 in the corresponding world, the subpage AP bits are disabled and the page tables have support for ARMv6 MMU features. Four new page table bits are added to support these features:
The Not-Global (nG) bit, determines if the translation is marked as global (0), or process-specific (1) in the TLB. For process-specific translations the translation is inserted into the TLB using the current ASID, from the ContextID Register, CP15 c13.
The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1) memory. This only applies to Normal memory regions. Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits.
The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable (1).
Three access permission bits. The access permissions extension (APX) bit, provides an extra access permission bit.
All ARMv6 page table mappings support the TEX field.
With the sub-pages enabled or not, all first level descriptors have been enhanced with the addition of the NS Attribute bit to enable the support of TrustZone.
Figure 6.7 shows the format of an ARMv6 first-level descriptor when subpages are disabled.
If the P bit is supported and set for the memory region, it indicates to the system memory controller that this memory region has ECC enabled. ARM1176JZ-S processors do not support the P bit. In addition to the invalid translation, bits [1:0] = b00, translations for the reserved entry, bits [1:0] = b11, result in a translation fault.
As shown in Figure 6.7, bits [1:0] of a level 1 page table entry determine the type of the entry:
Translation fault.
The entry points to a second-level page table, called a Coarse page table. Figure 6.8 shows the formats of the possible entries in the Coarse page table.
The entry points to a either a 1MB Section of memory or a 16MB Supersection of memory. Bit [18] of the descriptor selects between a Section and a Supersection. For details of supersections see Supersections.
You must repeat any Supersection description in 16 consecutive page table locations, with the first description occurring on a 16-word boundary. For more information see the ARM Architecture Reference Manual.
Reserved.
Figure 6.8 shows the format of an ARMv6 second-level descriptor.
As shown in Figure 6.8, bits [1:0] of a second-level descriptor determine the type of the descriptor:
Translation fault.
The entry points to a 64KB Large page in memory.
You must repeat any Large page description in 16 consecutive page table locations, with the first description occurring on a 16-word boundary. For more information see the ARM Architecture Reference Manual.
The entry points to a 4KB Extended small page in memory.
Bit [0] of the entry is the XN bit for the entry.
Figure 6.9 shows an overview of the section, supersection, and page translation process using ARMv6 descriptors.
| Copyright © 2004-2009 ARM Limited. All rights reserved. | ARM DDI 0333H |
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| Home > Memory Management Unit > Hardware page table translation > ARMv6 page table translation subpage AP bits disabled |