The values of ARADDRRW, ARBURSTRW, ARSIZERW,
and ARLENRW for Noncacheable
LDM6s addressing words 0 to 2 are shown in:
A Noncacheable LDM6 addressing words 3 to 7 is split into
two operations as shown in Table 8.29.
Table 8.27. Noncacheable LDM6, Strongly Ordered or Device memory
| Address[4:0] | ARADDRRW | ARBURSTRW | ARSIZERW | ARLENRW |
|---|
0x00, word 0 | 0x00 | Incr | 64-bit | 3 data transfers |
0x04, word 1 | 0x04 | Incr | 32-bit | 6 data transfers |
0x08, word 2 | 0x08 | Incr | 64-bit | 3 data transfers |
Table 8.28. Noncacheable LDM6, Noncacheable memory or cache disabled
| Address[4:0] | ARADDRRW | ARBURSTRW | ARSIZERW | ARLENRW |
|---|
0x00, word 0 | 0x00 | Incr | 64-bit | 3 data transfers |
0x04, word 1 | 0x04 | Incr | 64-bit | 4 data transfers |
0x08, word 2 | 0x08 | Incr | 64-bit | 3 data transfers |
Table 8.29. Noncacheable LDM6 from word 3, 4, 5, 6, or 7
| Address[4:0] | Operations |
|---|
0x0C, word 3 | LDM5 from 0x0C + LDR from 0x00 |
0x10, word 4 | LDM4 from 0x10 + LDM2 from 0x00 |
0x14, word 5 | LDM3 from 0x14 + LDM3 from 0x00 |
0x18, word 6 | LDM2 from 0x18 + LDM4 from 0x00 |
0x1C, word 7 | LDR from 0x1C + LDM5 from 0x00 |
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