14.3. ICode bus interface

The ICode interface is a 32-bit AHB-Lite bus interface. Instruction fetches and vector fetches from Code memory space (0x00000000 - 0x1FFFFFFF) are performed over this bus.Only the CM3Core instruction fetch bus can access the ICode interface, enabling optimal code fetch performance. All fetches are word wide. The number of instructions fetched per word depends on the code running and the alignment of the code in memory. Table 14.1 describes this.

Note

It is strongly recommended that any external arbitration between the I-Code and D-Code AHB bus interfaces ensures that D-Code has a higher priority than I-Code.

Table 14.1. Instruction fetches

32-bit instruction fetch [31:16]32-bit instruction fetch [15:0]Description
Thumb[15:0]Thumb[15:0]All Thumb instructions are halfword aligned in memory, so two Thumb instructions are fetched at a time. For sequential code, an instruction fetch is performed every second cycle. Instruction fetches can be performed on back-to-back cycles if there is an interrupt or a branch.
Thumb-2[31:16]Thumb-2[15:0]If Thumb-2 code is word-aligned in memory, then a complete Thumb-2 instruction is fetched each cycle.
Thumb-2[15:0]Thumb-2[31:16]If Thumb-2 code is halfword aligned, then the first 32-bit fetch only returns the first halfword of the Thumb-2 instruction. A second fetch must be performed to fetch the second halfword. This scenario creates a wait cycle (a cycle where CM3Core is not able to execute an instruction) depending on the instruction in play. The additional cycle of latency only occurs for the first halfword aligned Thumb-2 instruction fetch. CM3Core contains a 3-entry fetch buffer, and so the upper halfword of halfword aligned Thumb-2 instructions exist in the fetch buffer for subsequent sequential Thumb-2 instructions.

All ICode instruction fetches are marked as cacheable and non-bufferable, HPROTI[3:2] = 2'b10, and as allocate and non-shareable, MEMATTRI = 2'b01. These attributes are hard wired. If an MPU is fitted, the MPU region attributes are ignored for the ICode bus.

HPROTI[0] indicates what is being fetched:

All ICode transactions are performed as non-sequentials.

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337E
Non-Confidential