A.6. DCode interface

Table A.6 lists the signals of the DCode interface.

Table A.6. DCode interface

HADDRD[31:0]Output32-bit data address bus
HTRANSD[1:0]OutputIndicates whether the current transfer is IDLE, NONSEQUENTIAL, or SEQUENTIAL.
HWRITEDOutputWrite not read
HSIZED[2:0]OutputIndicates the size of the access. Can be 8, 16, or 32 bits.
HBURSTD[2:0]OutputIndicates if the transfer is part of a burst. Data accesses are performed as INCR on Cortex-M3.
HPROTD[3:0]OutputProvides information on the access. Always indicates cacheable and non-bufferable on this bus.
EXREQD-Exclusive request.

Memory attributes.

Always 01 for this bus (non-shareable, allocate).


Indicates the current D-Code bus master:

  • 0 = Core data side accesses.

  • 1 = DAP accesses.

  • 2 = Core instruction side accesses. These include vector fetches that are marked as data by HPROTD[0]. This value cannot appear on HMASTERD.

  • 3 = Reserved. This value cannot appear on HMASTERD.

HWDATAD[31:0]InputData read bus.
HREADYDInputWhen HIGH indicates that a transfer has completed on the bus. This signal is driven LOW to extend a transfer.
HRESPD[1:0]InputThe transfer response status. OKAY or ERROR.
HRDATAD[31:0]InputRead data.
EXRESPDInputExclusive response.
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