16.3. Branch status interface

The branch status signal, BRCHSTAT, gives fetch time information about the opcode in decode and the next execute. Decode time branches implicitly have a fetch cycle associated with them, so BRCHSTAT is only incident with the memory transaction in question. Execute time branches might have multicycle BRCHSTAT, which is dependent on the stall of the preceding opcode in execute. Table 16.2 describes the signal function.

Table 16.2. Branch status signal function

NameDirectionDescription
BRCHSTATOutput

0000 = No hint

0001 = Conditional branch backwards in decode[1]

0010 = Conditional branch in decode[2]

0011 = Conditional branch in execute[3]

0100 = Unconditional branch in decode[4]

0101 = Unconditional branch in execute[5]

0110 = Reserved

0111 = Reserved

1000 = Conditional branch in decode taken, cycle after IHTRANS of b0001 or b0010[6]

[1] T1B1 backwards or T2B0 backwards, not in IT block.

[2] T1B1 forwards or T2B0 forwards, not in IT block. T1B1 or T2B0 in IT block. T1B2 or T1MOV LR or T2BLX LR in IT block.

[3] T1CBZ. T1BLX !LR in IT block. T1MOV !LR in IT block.

[4] T1B2 or T2BL or T1MOV LR or T2BLX LR not in IT block.

[5] T1BLX !LR not in IT block. T1MOV !LR not in IT block.

[6] Asserted only in the cycle after b0001 and b0010.

Note

  • T1B1 and T2B0 are conditional branches

  • T1B2 and T2BL are unconditional branches

  • T1CBZ is a compare zero and branch.

Note

  • The encoding b1000 is only asserted in the cycle after conditional decode branches if the branch is taken. This is a registered output, so could be used to drive a mux of addresses in the memory controller.

  • The ALU register based branches and LSU PC modifying opcodes fall under b0101, except in IT blocks where they fall under b0011.

  • Multicycle LSU in the b0101 encoding suppresses fetches during execute.

  • Execute encodings are present for the multicycle duration of the decode.

Figure 16.1 and Figure 16.2 show a conditional branch backwards not taken and taken. The branch occurs speculatively in the decode phase of the opcode. The branch target is a halfword unaligned 16-bit opcode.

Figure 16.1. Conditional branch backwards not taken

Figure 16.2. Conditional branch backwards taken

Note

HADDRICore and HTRANSICore are the address and transaction request signals from the processor, and not the signals on the external Cortex-M3 interface.

Figure 16.3 and Figure 16.4 show a conditional branch forwards not taken and taken. The branch occurs speculatively in the decode phase of the opcode. The branch target is a halfword unaligned 16-bit opcode.

Figure 16.3. Conditional branch forwards not taken

Figure 16.4. Conditional branch forwards taken

Figure 16.5 and Figure 16.6 show an unconditional branch in this cycle, during the execute phase of the preceding opcode without and with pipeline stalls. The branch occurs in the decode phase of the opcode. The branch target is an aligned 32-bit opcode.

Figure 16.5. Unconditional branch without pipeline stalls

Figure 16.6. Unconditional branch with pipeline stalls

Figure 16.7 and Figure 16.8 show an unconditional branch in the next opcode. The branch occurs in the execute phase of the opcode. The branch target is an aligned and unaligned 32-bit ALU opcode.

Figure 16.7. Unconditional branch in execute aligned

Figure 16.8. Unconditional branch in execute unaligned

Table 16.3 shows an example of an opcode sequence.

Table 16.3. Example of an opcode sequence

Execute cycleFetch addressOpcode
10x1020ADD r1,#1
20x1022LDR r3,[r4]
30x1024ADD r2,#3
40x1026CMP r3,r2
50x1028BEQ = Target1
60x1040CMP r1,r2
70x1042ITE     // folded
80x1044LDR r3,[r4,r1]
90x1046LDR r3,[r4,r2]     // not taken
100x1048ADD r6,r3
110x104ANOP     // folded
120x104CBX r14
130x0FC4CMP
140x0FC6BEQ = Target2     // not taken
150x0FC8BX r5

Figure 16.9shows the timing sequence for the example opcode sequence in Table 16.3.

Figure 16.9. Example of an opcode sequence

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