14.5.6. Pipelined instruction fetches

To provide a clean timing interface on the System bus, instruction and vector fetch requests to this bus are registered. This results in an additional cycle of latency because instructions fetched from the System bus take two cycles. This also means that back-to-back instruction fetches from the System bus are not possible.


Instruction fetch requests to the ICode bus are not registered. Performance critical code must run from the ICode interface.

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